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ML7396AB Datasheet(PDF) 120 Page - LAPIS Semiconductor Co., Ltd. |
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ML7396AB Datasheet(HTML) 120 Page - LAPIS Semiconductor Co., Ltd. |
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120 / 140 page ![]() FEDL7396A/B/E-07 ML7396A/B/E 120/140 ○ RX During RX, if PLL unlock is detected, PLL unlock interrupt (INT[25] group4) will be generated. During RX, even if PLL unlock is detected, RX_ON state is maintained (do not move to IDLE state). Before next RX operation, issuing PHY reset by [RST_SET:B0 0x01] register and clearing PLL unlock interrupt should be required. START RX_ON issue [RF_STATUS:B0 0x6C] No PLL unlock (INT[25])? [INT_SOURCE_GRP4:B0 0x27] Yes PHY reset issue Normat RX [RST_SET:B0 0x01] Go to RX flowchart Clear INT[25] [INT_SOURCE_GRP4:B0 0x27] Yes Next packet RX? No END |
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