DS2155 datasheet(153/262 Pages) DALLAS

153 / 262 page

DS2156

153 of 262

23.7 LIU Control Registers

LIC1

Line Interface Control 1

78h

Bit #

Name

EGL

JAS

JABDS

DJA

TPD

Default

Bit 0/Transmit Power-Down (TPD)

0 = powers down the transmitter and three-states the TTIP and TRING pins

1 = normal transmitter operation

Bit 1/Disable Jitter Attenuator (DJA)

0 = jitter attenuator enabled

1 = jitter attenuator disabled

Bit 2/Jitter Attenuator Buffer Depth Select (JABDS)

0 = 128 bits

1 = 32 bits (use for delay-sensitive applications)

Bit 3/Jitter Attenuator Select (JAS)

0 = place the jitter attenuator on the receive side

1 = place the jitter attenuator on the transmit side

Bit 4/Receive Equalizer Gain Limit (EGL). This bit controls the sensitivity of the receive equalizer.

T1 Mode

0 = -36dB (long haul)

1 = 15dB (limited long haul)

E1 Mode

0 = -10dB (short haul)

1 = -43dB (long haul)

Bits 5 to 7/Line Buildout Select (L0 to L2). When using the internal termination, the user needs only to select 000

for 75Ω operation or 001 for 120Ω operation below. This selects the proper voltage levels for 75Ω or 120Ω

operation. Using TT0 and TT1 of the LICR4 register, the user can then select the proper internal source

termination. Line buildouts 100 and 101 are for backwards compatibility with older products only.

E1 Mode

Application

N (1)

Return Loss

Rt (1) (Ω)

75Ω normal

1:2

120Ω normal

1:2

75Ω with high return loss*

1:2

21dB

6.2

120Ω with high return loss*

1:2

21dB

11.6

*TT0 and TT1 of LIC4 register must be set to 0 in this configuration.

DS2155 Datasheet(PDF) 153 Page - Dallas Semiconductor

DS2155 Datasheet(HTML) 153 Page - Dallas Semiconductor

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL