DS2155 datasheet(154/262 Pages) DALLAS

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DS2156

154 of 262

T1 Mode

Application

N (1)

Return Loss

Rt (1) (Ω)

DSX-1 (0ft to 133ft) / 0dB CSU

1:2

DSX-1 (133ft to 266ft)

1:2

DSX-1 (266ft to 399ft)

1:2

DSX-1 (399ft to 533ft)

1:2

DSX-1 (533ft to 655ft)

1:2

-7.5dB CSU

1:2

-15dB CSU

1:2

-22.5dB CSU

1:2

LIC2

Line Interface Control 2

79h

Bit #

Name

ETS

LIRST

IBPV

TUA1

JAMUX

—

SCLD

CLDS

Default

Bit 0/Custom Line Driver Select (CLDS). Setting this bit to a 1 redefines the operation of the transmit line

driver. When this bit is set to a 1 and LIC1.5 = LIC1.6 = LIC1.7 = 0, the device generates a square wave at the

TTIP and TRING outputs instead of a normal waveform. When this bit is set to a 1 and LIC1.5 = LIC1.6 = LIC1.7

¹ 0, the device forces TTIP and TRING outputs to become open-drain drivers instead of their normal push-pull

operation. This bit should be set to 0 for normal operation of the device.

Bit 1/Short-Circuit Limit Disable (ETS = 1) (SCLD). Controls the 50mA (RMS) current limiter.

0 = enable 50mA current limiter

1 = disable 50mA current limiter

Bit 2/Unused, must be set to 0 for proper operation

Bit 3/Jitter Attenuator Mux (JAMUX). Controls the source for JACLK.

0 = JACLK sourced from MCLK (2.048MHz or 1.544MHz at MCLK)

1 = JACLK sourced from internal PLL (2.048MHz at MCLK)

Bit 4/Transmit Unframed All Ones (TUA1). The polarity of this bit is set such that the device transmits an all-

ones pattern on power-up or device reset. This bit must be set to a 1 to allow the device to transmit data. The

transmission of this data pattern is always timed off of the JACLK.

0 = transmit all ones at TTIP and TRING

1 = transmit data normally

Bit 5/Insert BPV (IBPV). A 0-to-1 transition on this bit causes a single BPV to be inserted into the transmit data

stream. Once this bit has been toggled from a 0 to a 1, the device waits for the next occurrence of three consecutive

1s to insert the BPV. This bit must be cleared and set again for a subsequent error to be inserted.

Bit 6/Line Interface Reset (LIRST). Setting this bit from a 0 to a 1 initiates an internal reset that resets the clock

recovery state machine and recenters the jitter attenuator. Normally this bit is only toggled on power-up. Must be

cleared and set again for a subsequent reset.

Bit 7/E1/T1 Select (ETS)

0 = T1 mode selected

1 = E1 mode selected

DS2155 Datasheet(PDF) 154 Page - Dallas Semiconductor

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