| Electronic Components Datasheet Search |
|
DS2155 Datasheet(PDF) 168 Page - Dallas Semiconductor |
|
|
|||||||||||||||||||||||||||||
DS2155 Datasheet(HTML) 168 Page - Dallas Semiconductor |
|
168 / 262 page ![]() DS2156 168 of 262 24.2 UTOPIA Clock Modes When the UTOPIA backplane is enabled, the user can select from several clocking modes: full T1/E1, clear-channel E1, or fractional T1/E1. Because ATM bytes are byte-aligned in the frame, clear-channel mode is only available in E1 operation. See Table 24-A for the various register configurations. Figure 24-1 shows a simplified diagram of the clock, data, and sync connections between the framer and the UTOPIA block. Figure 24-1. UTOPIA Clocking Configurations 24.3 Full T1/E1 Mode and Clear-Channel E1 Mode In full T1/E1 mode, the framer is programmed to provide a constant clock (RCLK for the receiver and TCLK for the transmitter) to the UTOPIA block by setting CCR3.4 and CCR3.5 = 1. The framer also provides frame-sync pulses to the UTOPIA block. The UTOPIA block is programmed to use the clock and sync signals by setting U_TCR2.1 and U_RCR2.1 = 0. In this mode the UTOPIA block uses the sync signal to byte align the transmit data stream and locate the F-bit position in T1 operation and TS0 and TS16 in E1 operation. In T1 mode, the receive and transmit UTOPIA blocks always use the frame-sync pulse to gap out the F- bit position. In E1 mode, the transmit UTOPIA block can be programmed to gap out TS0 and TS16 by setting U_TCR1.3 = 0, or use the full 256 bits of the frame by setting U_TCR1.3 = 1. Using the full 256 bits of the frame is referred to as clear-channel mode and is only available in E1 mode. In full E1 mode, the receive UTOPIA block always uses the frame-sync pulse to gap out TS0 and TS16. In order for the receive UTOPIA block to operate in clear-channel mode, set U_RCR2.1 = 1 while in full clock mode or use the fractional mode of operation described in Section 24.4 with all channels selected. RECEIVE FRAMER RECEIVE UTOPIA BLOCK RCLK GAPPED CLOCK FRAME SYNC CLOCK SYNC TRANSMIT FRAMER TRANSMIT UTOPIA BLOCK TCLK GAPPED CLOCK FRAME SYNC CLOCK SYNC TCLK DATA DATA DATA DATA CCR3.4 CCR3.5 0 0 1 1 NETWORK UTOPIA BACKPLANE |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |