DS2155 datasheet(202/262 Pages) DALLAS

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DS2156

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26.3 BERT Register Descriptions

BC1

BERT Control Register 1

E0h

Bit #

Name

TINV

RINV

PS2

PS1

PS0

RESYNC

Default

Bit 0/Force Resynchronization (RESYNC). A low-to-high transition forces the receive BERT synchronizer to

resynchronize to the incoming data stream. This bit should be toggled from low to high whenever the host wishes

to acquire synchronization on a new pattern. Must be cleared and set again for a subsequent resynchronization.

Bit 1/Load Bit and Error Counters (LC). A low-to-high transition latches the current bit and error counts into

registers BBC1/BBC2/BBC3/BBC4 and BEC1/BEC2/BEC3 and clears the internal count. This bit should be

toggled from low to high whenever the host wishes to begin a new acquisition period. Must be cleared and set

again for subsequent loads.

Bits 2 to 4/Pattern Select Bits (PS0 to PS2)

PS2 PS1 PS0

Pattern Definition

Pseudorandom 2E7 - 1

Pseudorandom 2E11 - 1

Pseudorandom 2E15 - 1

Pseudorandom pattern QRSS. A 220 - 1 pattern with 14 consecutive zero

restrictions.

Repetitive pattern

Alternating word pattern

Modified 55 octet (Daly) pattern. The Daly pattern is a repeating 55 octet

pattern that is byte-aligned into the active DS0 time slots. The pattern is

defined in an ATIS (Alliance for Telecommunications Industry Solutions)

Committee T1 Technical Report Number 25 (November 1993).

Pseudorandom 2E9 - 1

Bit 5/Receive Invert-Data Enable (RINV)

0 = do not invert the incoming data stream

1 = invert the incoming data stream

Bit 6/Transmit Invert-Data Enable (TINV)

0 = do not invert the outgoing data stream

1 = invert the outgoing data stream

Bit 7/Transmit Pattern Load (TC). A low-to-high transition loads the pattern generator with the pattern that is to

be generated. This bit should be toggled from low to high whenever the host wishes to load a new pattern. Must be

cleared and set again for subsequent loads.

DS2155 Datasheet(PDF) 202 Page - Dallas Semiconductor

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