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MCP19124 Datasheet(PDF) 204 Page - Microchip Technology

Part # MCP19124
Description  Digitally-Enhanced Power Analog Synchronous Low-Side Dual-Loop PWM Controller
PDF  236 Pages
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Manufacturer  MICROCHIP [Microchip Technology]
Direct Link  http://www.microchip.com
Logo MICROCHIP - Microchip Technology

MCP19124 Datasheet(HTML) 204 Page - Microchip Technology

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MCP19124/5
DS20005619A-page 204
 2016 Microchip Technology Inc.
BTFSS
Bit Test f, Skip if Set
Syntax:
[ label ] BTFSS f,b
Operands:
0
 f  127
0
 b< 7
Operation:
skip if (f<b>) = 1
Status Affected:
None
Description:
If bit ‘b’ in register ‘f’ is ‘0’, the next
instruction is executed.
If bit ‘b’ is ‘1’, the next instruction
is discarded and a NOP is
executed instead, making this a
two-cycle instruction.
CALL
Call Subroutine
Syntax:
[ label ] CALL k
Operands:
0
 k 2047
Operation:
(PC)+ 1
 TOS,
k
 PC<10:0>,
(PCLATH<4:3>)
 PC<12:11>
Status Affected:
None
Description:
Call Subroutine. First, return
address (PC + 1) is pushed onto
the stack. The 11-bit immediate
address is loaded into PC bits
<10:0>. The upper bits of the PC
are loaded from PCLATH. CALL is
a two-cycle instruction.
CLRF
Clear f
Syntax:
[ label ] CLRF f
Operands:
0
 f  127
Operation:
00h
 (f)
1
 Z
Status Affected:
Z
Description:
The contents of register ‘f’ are
cleared and the Z bit is set.
CLRW
Clear W
Syntax:
[ label ] CLRW
Operands:
None
Operation:
00h
 (W)
1
 Z
Status Affected:
Z
Description:
W register is cleared. Zero (Z) bit
is set.
CLRWDT
Clear Watchdog Timer
Syntax:
[ label ] CLRWDT
Operands:
None
Operation:
00h
 WDT
0
 WDT prescaler,
1
 TO
1
 PD
Status Affected:
TO, PD
Description:
CLRWDT
instruction resets the
Watchdog Timer. It also resets the
prescaler of the WDT.
Bits TO and PD in the STATUS
register are set.
COMF
Complement f
Syntax:
[ label ] COMF
f,d
Operands:
0
 f  127
d
 [0,1]
Operation:
(f)
 (destination)
Status Affected:
Z
Description:
The contents of register ‘f’ are
complemented. If ‘d’ is ‘0’, the
result is stored in W. If ‘d’ is ‘1’,
the result is stored back in
register ‘f’.
DECF
Decrement f
Syntax:
[ label ] DECF f,d
Operands:
0
 f  127
d
 [0,1]
Operation:
(f) - 1
 (destination)
Status Affected:
Z
Description:
Decrement register ‘f’. If ‘d’ is ‘0’,
the result is stored in the W
register. If ‘d’ is ‘1’, the result is
stored back in register ‘f’.



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