MCP19124 datasheet(50/236 Pages) MICROCHIP

50 / 236 page

MCP19124/5

DS20005619A-page 50

 2016 Microchip Technology Inc.

6.11.2

MOSFET DRIVER DEAD TIME

As described in Section 6.8 “MOSFET Driver

Programmable Dead Time”, the MOSFET drive dead

time can be adjusted. The dead time can be set

independently for each driver from 16 ns to 256 ns in

increments of 16 ns using the DEADCON register.

Dead time can also be disabled for each driver

independently by setting the bypass bits PDRVBY and

SDRVBY in the PE1 register.

6.11.3

SECONDARY CURRENT POSITIVE

SENSE PULL-UP

A high-impedance pull-up on the ISP pin can be

configured by setting the ISPUEN bit in the PE1

VDD. Refer to Register 6-13 for details.

6.11.4

PWM STEERING

The MCP19124/5 have additional control circuitry to

allow open-loop repositioning of the output. The

PWMSTR_PEN bit enables a primary-only PWM signal

of fixed frequency and duty cycle to reposition the

output voltage up. The PWMSTR_SEN bit enables a

secondary-only PWM signal of fixed frequency and

duty cycle to reposition the output voltage down. When

repositioning output voltage down, the output

overvoltage protection must be active along with

PWMSTR_SEN for the PWM to pulse the SDRV.

Frequency and duty cycle are controlled through TMR2

registers PR2 and TMR1L. PWMSTPR_PEN and

PWMSTR_SEN should never be active at the same

time, therefore the PWMSTPR_PEN is the dominant

bit. For quasi-resonant operation during open-loop

repositioning, the DESAT comparator output should be

disabled with the CDSOE bit in the DEADCON register.

6.12

Analog and Digital Test Signal

Enable and Control

Various analog and digital test signals can be enabled

or disabled, as shown in the ABECON register. These

signals can be configured to GPA0. Setting the

DIGOEN bit enables the digital test signals to be

connected to GPA0. DSEL<2:0> select the digital

channels. Setting ANAOEN enables the analog test

signals to be connected to GPA0. If ANAOEN and

DIGOEN both get set, the DIGOEN bit takes priority.

When ANAOEN is not set, the analog test signals are

connected to the internal ADC. The analog test channel

selections are controlled through the ADCON0 register.

6.12.1

MOSFET DRIVER UNDERVOLTAGE

LOCKOUT SELECTION

The MOSFET gate drivers have internal undervoltage

protection that is controlled by the DRUVSEL bit in the

ABECON register. Since the gate drive supply is

provided externally through the VDR pin, the drivers are

capable of driving logic level FETs or higher 10V (13.5V

maximum) FETs. DRUVSEL defaults to clear, therefore

selecting a gate drive UVLO of 2.7V. Setting DRUVSEL

selects the higher 5.4V gate drive UVLO. Refer to

Section 4.2

“Electrical

Characteristics”

for

additional electrical specifications.

bit 6

SDRVEN: SDRV Gate Drive Enable bit

= SDRV gate drive is enabled

= SDRV gate drive is disabled

bit 5

PDRVBY: PDRV Dead Time Bypass bit

= PDRV dead time is bypassed

= PDRV dead time is not bypassed

bit 4

SDRVBY: SDRV Dead Time Bypass bit

= SDRV dead time is bypassed

= SDRV dead time is not bypassed

bit 3

Unimplemented: Read as ‘0’

bit 2

ISPUEN: ISP Weak Pull-Up Enable bit

= ISP weak pull-up is enabled

= ISP weak pull-up is disabled

bit 1

PWMSTR_PEN: PDRV PWM Steering bit

= Enables open-loop PWM control to the PDRV

= Disables open-loop PWM control to the PDRV

bit 0

PWMSTR_SEN: SDRV PWM Steering bit

= Enables open-loop PWM control to the SDRV

= Disables open-loop PWM control to the SDRV

PE1: ANALOG PERIPHERAL ENABLE1 CONTROL REGISTER (CONTINUED)

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