MCP19124 datasheet(9/236 Pages) MICROCHIP

9 / 236 page

 2016 Microchip Technology Inc.

DS20005619A-page 9

MCP19124/5

1.0

DEVICE OVERVIEW

The MCP19124/5 are highly integrated, mixed-signal

low-side synchronous controllers that operate from

4.5V to 42V. The family features individual analog

PWM control loops for both current regulation or

voltage regulation. These features along with an

integrated microcontroller core make this an ideal

device used for battery charging applications, LED

lighting systems and any other low-side switch PWM

applications. The MCP19124/5 devices are derived

from the MCP19114/5 Enhanced PWM Controllers with

the exception of some additional features along with an

additional analog control loop designed for voltage

regulation. Complete customization of device operating

parameters, start-up or shutdown profiles, protection

levels and fault handling procedures are accomplished

by setting digital registers using Microchip’s MPLAB® X

Integrated Development Environment software and

one of Microchip’s many in-circuit debugger and device

programmers.

The MCP19124/5 mixed-signal low-side synchronous

controllers feature integrated programmable input

UVLO/OVLO, programmable output overvoltage (OV),

two low-side gate drive outputs with independent

programmable dead time, programmable leading edge

blanking (four steps), programmable 6-bit slope

compensation

and

integrated

internal

programmable

oscillator

for

fixed-frequency

applications. If users decide to regulate voltage via EA2

voltage error amplifier and control loop, the output OV

is disabled. An integrated 8-bit reference voltage

(VREF) is used for setting output current. A separate

integrated 8-bit reference voltage (OVREF) is used to

set the voltage regulation set point or the overvoltage

protection set point. An internal comparator supports

quasi-resonant applications. Additional Capture and

Compare modules are integrated for additional control,

including enhanced dimming capability.

The MCP19124/5 devices contain two internal LDOs.

A5V LDO (VDD) is used to power the internal

processor and provide 5V externally. A 4V LDO (AVDD)

is used to power the internal analog circuitry. Either

VDD or AVDD can be connected internally to the 10 bit

Analog-to-Digital Converter reference input. The 5V

external output can be used to supply the gate drive.

An analog filter between the VDD output and the VDR

input is recommended when implementing a 5V gate

drive supplied from VDD. Two 4.7 µF capacitors are

recommended with one placed as close as possible to

VDD and one as close as possible to VDR, separated by

a 10

 isolation resistor. DO NOT exceed 10 µF on the

VDD. An external supply is required to implement

higher gate drive voltages.

By utilizing a Microchip Technology Incorporated

TC1240A voltage doubler supplied from VDD to provide

VDR, a 10V gate drive can be achieved.

The 4V LDO is used to power the internal analog

circuitry. The two low-side drivers can be used to

operate the power converter in bidirectional mode,

enabling the “shaping” of LED dimming current in LED

applications

developing

bidirectional

power

converters for battery-powered applications.

The

MCP19124

packaged

24-lead

4 mm x 4 mm QFN and offers an alternate-bonded

28-lead 5 mm x 5 mm QFN. The MCP19125 is

packaged in a 28-lead 5 mm x 5 mm QFN.

The ability for system designers to configure

application-specific features allows users of the

MCP19124/5 devices to save costly board real estate

and additional component costs. The General Purpose

Input/Output (GPIO) of the MCP19124/5 can be

configured to offer a status output:

• a device enable, to control an external switch

• a switching frequency synchronization output or

input

• and even a device status or “heartbeat” indicator.

With integrated features like output current adjustment

and

dynamic

output

voltage

positioning,

the

MCP19124/5 family has the best in-class performance

and highest integration level currently available.

Power trains supported by this architecture include but

are not limited to boost, flyback, quasi-resonant

flyback, SEPIC, Ćuk, etc.

Two low-side gate drivers are capable of sinking and

sourcing 1A at 10V VDR. With a 5V gate drive, the

driver is capable of 0.5A sink and source. The user has

the option to allow the VIN UVLO to shut down the

drivers by setting the UVLOEN bit. When this bit is not

set, the device drivers will ride through the UVLO

condition and continue to operate until VDR reaches the

gate drive UVLO value. This value is selectable at 2.7V

or 5.4V and is always enabled. An internal reset for the

microcontroller core is set to 2.0V. An internal

comparator module is used to sense the desaturation

of the flyback transformer to synchronize switching for

quasi-resonant applications.

The operating input voltage for normal device operation

ranges from 4.5V to 42V with an absolute maximum of

44V. The maximum transient voltage is 48V for 500 ms.

An I2C serial bus is used for device communications

from the PWM controller to the system.

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