MCP19124 datasheet(71/236 Pages) MICROCHIP

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 2016 Microchip Technology Inc.

DS20005619A-page 71

MCP19124/5

10.2.2

CORE REGISTERS

The core registers contain the registers that directly

affect the basic operation. The core registers can be

addressed from any bank. These registers are listed in

Table 10-1.

For

detailed

information,

refer

Table 10-2.

10.2.2.1

STATUS Register

The STATUS register contains:

• the arithmetic status of the ALU

• the Reset status

• the bank select bits for data memory (RAM)

The STATUS register can be the destination for any

instruction, like any other register. If the STATUS

the Z, DC or C bits, the write to these three bits is

disabled. These bits are set or cleared according to the

device logic. Furthermore, the TO and PD bits are not

writable. Therefore, the result of an instruction with the

STATUS register as destination may be different than

intended.

For example, CLRF STATUS will clear the upper three

bits and set the Z bit. This leaves the STATUS register

as ‘000u u1uu’ (where u = unchanged).

It is recommended, therefore, that only BCF, BSF,

SWAPF

and MOVWF instructions are used to alter the

STATUS register, because these instructions do not

affect any Status bits.

TABLE 10-1: CORE REGISTERS

Addresses

BANKx

x00h, x80h, x100h, or x180h

INDF

x02h, x82h, x102h, or x182h

PCL

x03h, x83h, x103h, or x183h

STATUS

x04h, x84h, x104h, or x184h

FSR

x0Ah, x8Ah, x10Ah, or x18Ah

PCLATH

x0Bh, x8Bh, x10Bh, or x18Bh

INTCON

Note 1: The C and DC bits operate as Borrow

and Digit Borrow out bits, respectively, in

subtraction.

STATUS: STATUS REGISTER

R/W-0

R-1

R/W-x

IRP

RP1

RP0

DC (1)

C (1)

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n = Value at POR

x = Bit is unknown

‘0’

= Bit is cleared

‘1’

= Bit is set

bit 7

IRP: Register Bank Select bit (used for Indirect addressing)

= Bank 2 & 3 (100h - 1FFh)

= Bank 0 & 1 (00h - FFh)

bit 6-5

RP<1:0>: Register Bank Select bits (used for Direct addressing)

= Bank 0 (00h - 7Fh)

= Bank 1 (80h - FFh)

= Bank 2 (100h - 17Fh)

= Bank 3 (180h - 1FFh)

bit 4

TO: Time-Out bit

= After power-up, CLRWDT instruction or SLEEP instruction

= A WDT time-out occurred

Note 1: For Borrow, the polarity is reversed. A subtraction is executed by adding the two’s complement of the

second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high-order or

low-order bit in the source register.

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