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MCP19124 Datasheet(PDF) 75 Page - Microchip Technology |
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MCP19124 Datasheet(HTML) 75 Page - Microchip Technology |
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75 / 236 page  TABLE 10-3: MCP19124/5 SPECIAL REGISTERS SUMMARY BANK 1 Addr. Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR Reset Values on all other resets (1) Bank 1 80h INDF Addressing this location uses contents of FSR to address data memory (not a physical register) xxxx xxxx uuuu uuuu 81h OPTION_REG RAPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111 82h PCL Program Counter's (PC) Least Significant byte 0000 0000 0000 0000 83h STATUS IRP RP1 RP0 TO PD ZDC C 0001 1xxx 000q quuu 84h FSR Indirect data memory address pointer xxxx xxxx uuuu uuuu 85h TRISGPA TRISA7 TRISA6 TRISA5 — TRISA3 TRISA2 TRISA1 TRISA0 1110 1111 1110 1111 86h TRISGPB TRISB7 TRISB6 TRISB5 TRISB4 — — TRISB1 TRISB0 1111 0011 1111 0011 87h PIE1 — — BCLIE SSPIE CC2IE CC1IE TMR2IE TMR1IE --00 0000 --00 0000 88h PIE2 CDSIE ADIE — OTIE OVIE DRUVIE OVLOIE UVLOIE 00-0 0000 00-0 0000 89h — Unimplemented — — 8Ah PCLATH — — — Write buffer for upper 5 bits of program counter ---0 0000 ---0 0000 8Bh INTCON GIE PEIE T0IE INTE IOCE T0IF INTF IOCF (2) 0000 000x 0000 000u 8Ch — Unimplemented — — 8Dh — Unimplemented — — 8Eh — Unimplemented — — 8Fh — Unimplemented — — 90h VINUVLO — — UVLO5 UVLO4 UVLO3 UVLO2 UVLO1 UVLO0 --xx xxxx --uu uuuu 91h VINOVLO — — OVLO5 OVLO4 OVLO3 OVLO2 OVLO1 OVLO0 --xx xxxx --uu uuuu 92h VINCON UVLOEN UVLOOUT UVLOINTP UVLOINTN OVLOEN OVLOOUT OVLOINTP OVLOINTN 0x00 0x00 0u00 0u00 93h CC1RL Capture1/Compare1 Register1 x Low Byte (LSB) xxxx xxxx uuuu uuuu 94h CC1RH Capture1/Compare1 Register2 x High Byte (MSB) xxxx xxxx uuuu uuuu 95h CC2RL Capture2/Compare2 Register1 x Low Byte (LSB) xxxx xxxx uuuu uuuu 96h CC2RH Capture2/Compare2 Register2 x High Byte (MSB) xxxx xxxx uuuu uuuu 97h CCDCON CC2M<3:0> CC1M<3:0> xxxx xxxx uuuu uuuu 98h DESATCON CDSMUX CDSWDE Reserved CDSPOL CDSOE CDSOUT CDSINTP CDSINTN 0000 0x00 0000 0u00 99h OVCON — — — — OVEN OVOUT OVINTP OVINTN ---- 0x00 ---- 0u00 9Ah OVREFCON OOV7 OOV6 OOV5 OOV4 OOV3 OOV2 OOV1 OOV0 xxxx xxxx uuuu uuuu 9Bh DEADCON PDRVDT3 PDRVDT2 PDRVDT1 PDRVDT0 SDRVDT3 SDRVDT2 SDRVDT1 SDRVDT0 xxxx xxxx uuuu uuuu 9Ch SLPCRCON — SLPBY SLPS5 SLPS4 SLPS3 SLPS2 SLPS1 SLPS0 -xxx xxxx -uuu uuuu 9Dh ICOACON — — — — ICOAC3 ICOAC2 ICOAC1 ICOAC0 ---- xxxx ---- uuuu 9Eh ICLEBCON — — — — — — ICLEBC1 ICLEBC0 ---- --xx ---- --uu 9Fh — Unimplemented — — Legend: — = Unimplemented locations read as ‘0’, u = unchanged, x = unknown, q = value depends on condition, shaded = unimplemented Note 1: Other (non power-up) resets include MCLR Reset and Watchdog Timer Reset during normal operation. 2: MCLR and WDT reset does not affect the previous value data latch. The IOCF bit will be cleared upon reset but will be set again if the mismatch exists. |
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