MCP19124 datasheet(15/236 Pages) MICROCHIP

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 2016 Microchip Technology Inc.

DS20005619A-page 15

MCP19124/5

2.1

Detailed Pin Functional

Description

2.1.1

GPA0 PIN

GPA0 is a general-purpose TTL input or CMOS output

pin whose data direction is controlled in TRISGPA. An

internal weak pull-up and interrupt-on-change are also

available.

AN0 is an input to the A/D. To configure this pin to be

read by the A/D on channel 0, bits TRISA0 and ANSA0

must be set.

The ABECON register can be configured to set this pin

to the TEST_OUT function. It is a buffered output of the

internal analog or digital signal multiplexers. Analog

signals present on this pin are controlled by the

ADCON0 register. Digital signals present on this pin

are controlled by the ABECON register.

2.1.2

GPA1 PIN

GPA1 is a general-purpose TTL input or CMOS output

pin whose data direction is controlled in TRISGPA. An

internal weak pull-up and interrupt-on-change are also

available.

AN1 is an input to the A/D. To configure this pin to be

read by the A/D on channel 1, bits TRISA1 and ANSA1

must be set.

When the MCP19124/5 are configured as a master or

slave, this pin can be configured to be the switching

frequency synchronization input or output (CLKPIN).

2.1.3

GPA2 PIN

GPA2 is a general-purpose ST input or CMOS output

pin whose data direction is controlled in TRISGPA. An

internal weak pull-up and interrupt-on-change are also

available.

AN2 is an input to the A/D. To configure this pin to be

read by the A/D on channel 2, bits TRISA2 and ANSA2

must be set.

When bit T0CS is set in the OPTION_REG register, the

T0CKI function is enabled. Refer to Section 21.0

“Timer0 Module” for more information.

GPA2 can also be configured as an external interrupt

by setting the INTE bit. Refer to Section 13.2

“GPA2/INT Interrupt” for more information.

2.1.4

GPA3 PIN

GPA3 is a general-purpose TTL input or CMOS output

pin whose data direction is controlled in TRISGPA. An

internal weak pull-up and interrupt-on-change are also

available.

AN3 is an input to the A/D. To configure this pin to be

read by the A/D on channel 3, bits TRISA3 and ANSA3

must be set.

2.1.5

GPA5 PIN

GPA5 is a general-purpose TTL input only pin. An

internal weak pull-up and interrupt-on-change are also

available.

For programming purposes, this pin is to be connected

to the MCLR pin of the serial programmer. Refer to

Section 30.0 “In-Circuit Serial Programming™

(ICSP™)” for more information.

This pin is MCLR when the MCLRE bit is set in the

CONFIG register.

2.1.6

GPA6 PIN

GPA6 is a general-purpose CMOS output ST input pin

whose data direction is controlled in TRISGPA.

ICSPDAT is a serial programming data I/O function.

This can be used in conjunction with ICSPCLK to serial

program the device.

GPA6 is part of the CCD Module. For more information,

refer to Section 24.0 “Dual Capture/Compare (CCD)

Module”.

2.1.7

GPA7 PIN

GPA7 is a true open drain general-purpose pin whose

data direction is controlled in TRISGPA. There is no

internal connection between this pin and device VDD.

This pin does not have a weak pull-up, but inter-

rupt-on-change is available.

This pin is the primary ICSPCLK input. This can be

used in conjunction with ICSPDAT to serial program

the device.

When the MCP19124/5 is configured for I2C

communication, Section 28.2 “I2C Mode Overview”,

GPA7 functions as the I2C clock (SCL). This pin must

be configured as an input to allow proper operation.

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