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MCP19124 Datasheet(PDF) 3 Page - Microchip Technology |
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MCP19124 Datasheet(HTML) 3 Page - Microchip Technology |
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3 / 236 page  2016 Microchip Technology Inc. DS20005619A-page 3 MCP19124/5 TABLE 1: 24-PIN QFN (MCP19124) SUMMARY Basic Additional GPA0 1 Y AN0 — — IOC Y — Analog/Digital Debug Output (1) GPA1 2 Y AN1 — — IOC Y — Sync Signal In/Out (2) GPA2 3 Y AN2 T0CKI — IOC INT Y — — GPA3 4 Y AN3 — — IOC Y — — GPA5 7 N — — — IOC (3) Y (4) MCLR Test Enable Input GPA6 6 N — — — IOC Y ICSPDAT Dual Capture/Compare Input GPA7 5 N — — SCL IOC N ICSPCLK — GPB0 8 N — — SDA IOC N — — GPB1 24 Y AN4 — — IOC Y — VREF2 (5) DESATN 9 N — — — — — — DESAT Negative Input DESATP 10 N — — — — — — DESAT Positive Input ISP 11 N — — — — Y — Current Sense Amplifier Positive Input ISN 12 N — — — — — — Current Sense Amplifier Negative Input IP 13 N — — — — — — Primary Input Current Sense AGND 14 N — — — — — AGND Small Signal Ground PGND 15 N — — — — — PGND Large Signal Ground SDRV 16 N — — — — — — Secondary LS Gate Drive Output PDRV 17 N — — — — — — Primary LS Gate Drive Output VDR 18 N — — — — — VDR Gate Drive Supply Voltage VDD 19 N — — — — — VDD VDD Output VIN 20 N — — — — — VIN Input Supply Voltage VS 21 N — — — — — — Output Voltage Sense VCOMP 22 N — — — — — — EA2 Voltage Error Amplifier Output ICOMP 23 N — — — — — — EA1 Current Error Amplifier Output EXP 25 N — — — — — — Exposed Thermal Pad Note 1: The Analog/Digital Debug Output is selected through the control of the ABECON register. 2: Selected when functioning as master or slave by proper configuration of the MSC<1:0> bits in the MODECON register. 3: The IOC is disabled when MCLR is enabled. 4: Weak pull-up always enabled when MCLR is enabled, otherwise the pull-up is under user control. 5: VREF2 output selected when configured as master by proper configuration of the MSC<1:0> bits in the MODECON register. |
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