LAN89218 datasheet(123/148 Pages) MICROCHIP

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DS60001255B-page 123

LAN89218

6.0

TIMING DIAGRAMS

6.1

Host Interface Timing

The LAN89218 supports the following host cycles:

Read Cycles:

• PIO Reads (nCS or nRD controlled)

• PIO Burst Reads (nCS or nRD controlled)

• RX Data FIFO Direct PIO Reads (nCS or nRD controlled)

• RX Data FIFO Direct PIO Burst Reads (nCS or nRD controlled)

Write Cycles:

• PIO writes (nCS and nWR controlled)

• TX Data FIFO direct PIO writes (nCS or nWR controlled)

6.1.1

SPECIAL RESTRICTIONS ON BACK-TO-BACK WRITE/READ CYCLES

It is important to note that there are specific restrictions on the timing of back-to-back write-read operations. These

restrictions concern reading the control registers after any write cycle to the LAN89218 device. In many cases there

is a required minimum delay between writing to the LAN89218, and the subsequent side effect (change in the control

in the TX_FIFO_INF register.

In order to prevent the host from reading stale data after a write operation, minimum wait periods must be enforced.

These periods are specified in Table 6-1. The host processor is required to wait the specified period of time after any

write to the LAN89218 before reading the resource specified in the table. These wait periods are for read operations

that immediately follow any write cycle. Note that the required wait period is dependent upon the register being read

after the write.

Performing "dummy" reads of the BYTE_TEST register is a convenient way to guarantee that the minimum write-to-

read timing restriction is met. Table 6-1 also shows the number of dummy reads that are required before reading the

For microprocessors with slower buses the number of reads may be reduced as long as the total time is equal to,

or greater than the time specified in the table. Note that dummy reads of the BYTE_TEST register are not required

as long as the minimum time period is met.

Note:

Unless otherwise noted, timing specifications assume a load capacitance of 25 pF and are valid over the

operating conditions specified in Section 7.2.

TABLE 6-1:

READ AFTER WRITE TIMING RULES

Minimum Wait Time for Read Following

Any Write Cycle (in ns)

Number of BYTE_TEST Reads

(Assuming tcycle of 45 ns)

ID_REV

IRQ_CFG

135

INT_STS

INT_EN

BYTE_TEST

FIFO_INT

RX_CFG

TX_CFG

HW_CFG

RX_DP_CTRL

RX_FIFO_INF

TX_FIFO_INF

135

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