LAN89218 datasheet(124/148 Pages) MICROCHIP

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LAN89218

DS60001255B-page 124

 2008-2015 Microchip Technology Inc.

6.1.2

SPECIAL RESTRICTIONS ON BACK-TO-BACK READ CYCLES

There are also restrictions on specific back-to-back read operations. These restrictions concern reading specific

registers after reading resources that have side effects. In many cases there is a delay between reading the

LAN89218, and the subsequent indication of the expected change in the control register values.

In order to prevent the host from reading stale data on back-to-back reads, minimum wait periods have been

established. These periods are specified in Table 6-2. The host processor is required to wait the specified period of

time between read operations of specific combinations of resources. The wait period is dependent upon the

combination of registers being read.

Performing "dummy" reads of the BYTE_TEST register is a convenient way to guarantee that the minimum wait time

restriction is met. Table 6-2 also shows the number of dummy reads that are required for back-to-back read

operations. The number of BYTE_TEST reads in this table is based on the minimum timing for Tcycle (45 ns). For

microprocessors with slower buses the number of reads may be reduced as long as the total time is equal to, or

greater than the time specified in the table. Dummy reads of the BYTE_TEST register are not required as long as

the minimum time period is met.

PMT_CTRL

315

GPIO_CFG

GPT_CFG

GPT_CNT

135

WORD_SWAP

FREE_RUN

180

RX_DROP

MAC_CSR_CMD

MAC_CSR_DATA

AFC_CFG

E2P_CMD

E2P_DATA

TABLE 6-2:

READ AFTER READ TIMING RULES

After Reading...

Wait for this many

... ns

or Perform This Many Reads

of BYTE_TEST…

(Assuming tcycle of 45 ns)

Before Reading ...

RX Data FIFO

135

RX_FIFO_INF

RX Status FIFO

135

RX_FIFO_INF

TX Status FIFO

135

TX_FIFO_INF

RX_DROP

180

RX_DROP

TABLE 6-1:

READ AFTER WRITE TIMING RULES (CONTINUED) (CONTINUED)

Minimum Wait Time for Read Following

Any Write Cycle (in ns)

Number of BYTE_TEST Reads

(Assuming tcycle of 45 ns)

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