LAN89218 datasheet(125/148 Pages) MICROCHIP

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DS60001255B-page 125

LAN89218

6.2

PIO Reads

PIO reads can be used to access CSRs or RX Data and RX/TX status FIFOs. In this mode, counters in the CSRs

are latched at the beginning of the read cycle. Read data is valid as indicated in the timing diagram. PIO reads can

be performed using Chip Select (nCS) or Read Enable (nRD). Either or both of these control signals must go high

between cycles for the period specified.

PIO reads are supported for both 16- and 32-bit access. Timing for 16-bit and 32-bit PIO Read cycles is identical

with the exception that D[31:16] are not driven during a 16-bit read.

Note:

Some registers have restrictions on the timing of back-to-back, write-read and read-read cycles.

FIGURE 6-1:

PIO READ CYCLE TIMING

Note:

The “Data Bus” width is 32 bits with optional support for 16-bit bus widths.

TABLE 6-3:

PIO READ TIMING

Symbol

Description

Min.

Typ.

Max.

Unit

tcycle

Read Cycle Time

tcsl

nCS, nRD Assertion Time

tcsh

nCS, nRD Deassertion Time

tcsdv

nCS, nRD Valid to Data Valid

tasu

Address, END_SEL Setup to nCS, nRD Valid

tah

Address, END_SEL Hold Time

tdon

Data Buffer Turn On Time

tdoff

Data Buffer Turn Off Time

tdoh

Data Output Hold Time

Note:

A PIO Read cycle begins when both nCS and nRD are asserted. The cycle ends when either or both nCS

and nRD are deasserted. They may be asserted and deasserted in any order.

tah

A[7:1], END_SEL

nCS, nRD

Data Bus

tasu

tcycle

tcsh

tcsl

tcsdv

tdon

tdoh

tdoff

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