AT49LW080 datasheet(8/34 Pages) ATMEL

8 / 34 page

AT49LW080/040

1966C–FLASH–03/02

Device Operation

READ: Read operations consist of preamble, TAR, SYNC and data fields as shown in

Figure 2 and described in Table 5. TAR and SYNC fields are described below. Com-

mands using the read mode include the following functions: reading memory from the

array, reading the identifier codes, reading the lock bit registers and reading the GPI

registers. Memory information, identifier codes, or the GPI registers can be read inde-

pendent of the VPP voltage. Upon initial device power-up or after exit from reset mode,

the device automatically resets to read array mode.

READ CYCLE, SINGLE BYTE: For read cycles, after the preamble, the master drives a

TAR field to give ownership of the bus to the FWH. After the second clock of the TAR

phase the FWH assumes the bus and begins driving SYNC values. When it is ready, it

drives the low nibble, then the high nibble of data, followed by a TAR field to give control

back to the master.

Figure 2 shows a device that requires three SYNC clocks to access data. Since the

access time can begin once the address phase has been completed, the two clocks of

the TAR phase can be considered as part of the access time of the part. For example, a

device with a 120 ns access time could assert “0101b” for clocks 1 and 2 of the SYNC

phase and “0000b” for the last clock of the SYNC phase. This would be equivalent to

five clocks worth of access time if the device started that access at the conclusion of the

preamble phase. Once SYNC is achieved, the device then returns the data in two clocks

and gives ownership of the bus back to the master with a TAR phase.

TURN-AROUND (TAR): This field is two clocks wide, and is driven by the master when

it is turning control over to the FWH, (for example, to read data), and is driven by the

FWH when it is turning control back over to the master. On the first clock of this

two-clock-wide field, the master or FWH drives the FWH[3:0] lines to “1111b”. On the

second clock of this field, the master or peripheral tri-states the FWH[3:0] lines.

SYNC: This field is used to add wait states. It can be several clocks in length. On target

or DMA cycles, this field is driven by the FWH. If the FWH needs to assert wait states, it

does so by driving “0101b” (short SYNC) on FWH[3:0] until it is ready. When ready, it

will drive “0000b”. Valid values for this field are shown in Table 4.

Figure 2. FWH Single-byte Read Waveforms

Table 4. Valid SYNC Values

Bits[3:0]

Indication

0000

Ready: SYNC achieved with no error.

0101

Short Wait: Part indicating wait states.

IDSEL

MADDR

MSIZE

TAR

SYNC(3)

TAR

DATA

CLK

FWH4

FWH[3:0]

PREAMBLE

START

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