AT49LW080 datasheet(18/34 Pages) ATMEL

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AT49LW080/040

1966C–FLASH–03/02

READ ARRAY: Upon initial device power-up and after exit from reset, the device

defaults to read array mode. This operation is also initiated by writing the Read Array

command. The device remains enabled for reads until another command is written.

Once the internal state machine (WSM) has started a block erase or program operation,

the device will not recognize the Read Array Command until the operation is completed,

unless the operation is suspended via an Erase Suspend or Program Suspend Com-

mand. The Read Array command functions independently of the VPP voltage.

PRODUCT IDENTIFICATION: The product identification mode identifies the device and

manufacturer as Atmel.

Following the Product ID Entry command, read cycles from the addresses shown in

Table 12 retrieve the manufacturer and device code. To exit the product identification

mode, any valid command can be written to the device. The Product ID Entry command

functions independently of the VPP voltage.

SECTOR ERASE: Beforeabytecan be programmed, it must beerased. Theerased

state of the memory bits is a logical “1”. Since the AT49LW080/040 does not offer a

complete chip erase, the device is organized into multiple sectors that can be individu-

ally erased. The Sector Erase command is a two-bus cycle operation. The sector whose

address is valid at the second falling edge of the WE will be erased, provided the given

sector is not protected.

Successful sector erase requires that the corresponding sector’sWrite Lockbit be

cleared and the corresponding write-protect pin (TBL or WP) be inactive.Ifsector erase

is attempted when the sector is locked, the sector erase will fail, with the reason for fail-

ure in the status register.

Successful sector erase only occurs when V

PP =VPPH1 or VPPH2. If the erase operation is

attempted at V

PP ≠ VPPH1 or VPPH2 erratic results may occur.

BYTE PROGRAMMING: The device is programmed on a byte-by-byte basis. Program-

ming is accomplished via the internal device command register and is a two-bus cycle

operation. The programming address and data are latched in the second bus cycle. The

device will automatically generate the required internal programming pulses. Please

note that a “0” cannot be programmed back to a “1”; only an erase operation can convert

“0”sto “1”s.

After the program command is written, the device automatically outputs the status regis-

ter data when read. When programming is complete, the status register may be

checked. If a program error is detected, the status register should be cleared before cor-

rective action is taken by the software. The internal WSM verification Error Checking

only detects “1”s that do not successfully program to “0”s.

Reliable programming only occurs when V

PP =VPPH1 or VPPH2. If the program operation

is attempted at V

PP ≠ VPPH1 or VPPH2 erratic results may occur.

A successful program operation also requires that the corresponding sector’s Write Lock

bit be cleared, and the corresponding write-protect pin (TBL or WP) be inactive. If a pro-

gram operation is attempted when the sector is locked, the operation will fail.

Table 12. Identifier Codes

Code

Address (AID)

Data

Manufacturer Code

000000

Device Code

AT49LW040

000001

AT49LW080

000001

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