AT49LW080 datasheet(9/34 Pages) ATMEL

9 / 34 page

AT49LW080/040

1966C–FLASH–03/02

Note:

1. Field contents are valid on the rising edge of the present clock cycle.

Table 5. FWH Read Cycle

Clock Cycle

Field Name

Field Contents

(1)

FWH[3:0]

Direction

Comments

START

1101b

FWH4 must be active (low) for the part to respond.

Only the last start field (before FWH4 transitioning

high) should be recognized. The START field contents

indicate an FWH memory read cycle.

IDSEL

0000b

1111b

Indicates which FWH device should respond. If the

IDSEL (ID select) field matches the value ID[3:0],

then that particular device will respond to subsequent

commands.

3 - 9

MADDR

YYYY

These seven clock cycles make up the 28-bit memory

address. YYYY is one nibble of the entire address.

Addresses are transferred most significant nibble first.

MSIZE

0000b (1 byte)

The FWH will only support single-byte transfers.

TAR0

1111b

then float

In this clock cycle, the master (ICH) has driven the

bus to all 1s and then floats the bus, prior to the next

clock cycle. This is the first part of the bus “turnaround

cycle”.

TAR1

1111b (float)

Float then OUT

The FWH takes control of the bus during this cycle.

During the next clock cycle, it will be driving “sync

data”.

13 - 14

WSYNC

0101b (WAIT)

OUT

The FWH outputs the value 0101, a wait-sync

(WSYNC, a.k.a. “short-sync”), for two clock cycles.

This value indicates to the master (ICH) that data is

not yet available from the part. This number of wait-

syncs is a function of the device’s access time.

RSYNC

0000b (READY)

OUT

During this clock cycle, the FWH will generate a

“ready-sync” (RSYNC) indicating that the least

significant nibble of the least significant byte will be

available during the next clock cycle.

DATA

YYYY

OUT

YYYY is the least significant nibble of the least

significant data byte.

DATA

YYYY

OUT

YYYY is the most significant nibble of the least

significant data byte.

TAR0

1111b

OUT

then float

The FWH Flash memory drives FWH0 - FWH3 to

1111b to indicate a turnaround cycle.

TAR1

1111b (float)

Float then

The FWH Flash memory floats its outputs, the master

(ICH) takes control of FWH3 - FWH0.

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