AT49LW080 datasheet(6/34 Pages) ATMEL

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AT49LW080/040

1966C–FLASH–03/02

Firmware Hub

Interface (FWH)

Table 2 lists the seven required signals used for the FWH interface.

FWH[3:0]: The FWH[3:0] signal lines communicate address, control, and data informa-

ti on o ver th e LPC bu s betw een a m as te r an d a p eri ph era l. T he i nfo rm atio n

communicated are: start, stop (abort a cycle), transfer type (memory, I/O, DMA), trans-

fer direction (read/write), address, data, wait states, DMA channel, and bus master

grant.

FWH4: FWH4 is used by the master to indicate the start of cycles and the termination of

cycles due to an abort or time-out condition. This signal is to be used be by peripherals

to know when to monitor the bus for a cycle.

The FWH4 signal is used as a general notification that the FWH[3:0] lines contain infor-

mation relative to the start or stop of a cycle, and that peripherals must monitor the bus

to determine whether the cycle is intended for them. The benefit to peripherals of FWH4

is, it allows them to enter lower power states internally.

When peripherals sample FWH4 active, they are to immediately stop driving the

FWH[3:0] signal lines on the next clock and monitor the bus for new cycle information.

RESET: RST or INIT at VIL initiates a device reset. In read mode, RST or INIT low

deselects the memory, places output drivers in a high-impedance state, and turns off all

internal circuits. RST or INIT must be held low for time tPLPH (A/A Mux and FWH opera-

tion). The FWH resets to read array mode upon return from reset, and all sectors are set

to default (locked) status regardless of their locked state prior to reset.

Driving RST or INIT low resets the device, which resets the sector lock registers to their

default (write-locked) condition. A reset time (tPHQV A/A Mux) is required from RST or

INIT switching high until outputs are valid. Likewise, the device has a wake time (tPHRH

A/A Mux) from RST or INIT high until writes to the CUI are recognized. A reset latency

will occur if a reset procedure is performed during a programming or erase operation.

During sector erase or program, driving RST or INIT low will abort the operation under-

way, in addition to causing a reset latency. Memory contents being altered are no longer

valid, since the data may be partially erased or programmed.

It is important to assert RST or INIT during system reset. When the system comes out of

reset, it will expect to read from the memory array of the device. If a system reset occurs

with no FWH reset (this will be hardware dependent), it is possible that proper CPU ini-

tialization will not occur (the FWH memory may be providing status information instead

of memory array data).

Table 2. FWH Required Signal List

Signal

Direction

Description

Peripheral

Master

FWH[3:0]

I/O

Multiplexed command, address and data

FWH4

Indicates start of a new cycle, termination of broken

cycle.

RST

Reset: Same as PCI Reset on the master. The master

does not need this signal if it already has PCIRST on

its interface.

CLK

Clock: Same 33 MHz clock as PCI clock on the

master. Same clock phase with typical PCI skew. The

master does not need this signal if it already has

PCICLK on its interface.

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