AT49LW080 datasheet(3/34 Pages) ATMEL

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AT49LW080/040

1966C–FLASH–03/02

Block Diagram

Pin Description

Table 1 details the usage of each of the device pins. Most of the pins have dual function-

ality, with functions in both the Firmware Hub and A/A Mux interfaces. A/A Mux

functionality for pins is shown in bold in the description box for that pin. All pins are

designed to be compliant with voltage of VCC + 0.3V max, unless otherwise noted.

FWH

INTERFACE

A10 - A0

I/O7 - I/O0

FLASH

ARRAY

CONTROL

LOGIC

A/A MUX

INTERFACE

RST

CLK

FWH (4:0)

ID (3:0)

FGPI (4:0)

TBL

R/C

INIT

RY/BY

Table 1. Pin Description

Symbol

Type

Interface

Name and Function

FWH

A/A Mux

INPUT

INTERFACE CONFIGURATION PIN: This pin determines which interface

is operational. This pin is held high to enable the A/A Mux interface. This

pin is held low to enable the FWH interface. This pin must be set at

power-up or before return from reset and not changed during device

operation. This pin is pulled down with an internal resistor, with value

between 20 and 100 k

Ω. With IC high (A/A Mux mode), this pin will exhibit

a leakage current of approximately 200 µA. This pin may be floated,

which will select FWH mode.

RST

INPUT

INTERFACE RESET: Valid for both A/A Mux and FWH interface

operations. When driven low, RST inhibits write operations to provide

data protection during power transitions, resets internal automation, and

tri-states pins FWH [3:0] (in FWH interface mode). RST high enables

normal operation. When exiting from reset, the device defaults to read

array mode.

INIT

INPUT

PROCESSOR RESET: This is a second reset pin for in-system use. This

pin is internally combined with the RST pin. If this pin or RST is driven

low, identical operation is exhibited. This signal is designed to be

connected to the chipset INIT signal (Max voltage depends on the

processor. Do not use 3.3V.)

A/A Mux = OE

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