AT49LW080 datasheet(7/34 Pages) ATMEL

7 / 34 page

AT49LW080/040

1966C–FLASH–03/02

C Y C L E T YPES: T here a re tw o t y pes o f c y cl e s t hat a r e s up porte d b y t he

AT49LW080/040: FWH Memory Read and FWH Memory Write. FWH Memory Read or

Write cycles start with a preamble.

PREAMBLE: The preamble consists of a START, IDSEL, 28-bit Address and MSIZE

fields. The preamble is shown in Figure 1. The preamble begins with FWH4 going low

andaSTART fielddrivenonFWH[3:0]. ForFWH Memory Read cycles, the START field

must be 1101b; for FWH Memory Write cycles, the START field must be 1110b. Follow-

ing the START field is the IDSEL field. This field acts like a chip select in that it indicates

which device should respond to the current transaction. The next seven clocks are the

28-bit address, which tell from where to begin reading or writing in the selected device.

Next, an MSIZE value of 0 indicates the master is requesting a single byte.

Figure 1. FWH Memory Cycle Preamble

START: This one-clock field indicates the start of a cycle. It is valid on the last clock that

FWH4 is sampled low. The two start fields that are used for the cycle are shown in Table

3. If the start field that is sampled is not one of these values, then the cycle attempted is

not an FWH memory cycle. It may be a valid memory cycle that the FWH component

may wish to decode, i.e., it may be of the LPC memory cycle variety.

IDSEL (DEVICE SELECT): This one-clock field is used to indicate which FWH compo-

nent is being selected. The four bits transmitted over FWH[3:0] during this clock are

compared with values strapped onto pins [ID3:ID0] on the FWH component. If there is a

match, the FWH component will continue to decode the cycle to determine which bytes

are requested on a read or which bytes to update on a write. If there isn’t a match, the

FWH component may discard the rest of the cycle and go into a standby power state.

MADDR (MEMORY ADDRESS): This is a seven-clock field, which gives a 28-bit mem-

ory address. This allows for up to 256 MB per memory device, for a total of a 4 GB

addressable space. The address is transferred with the most significant nibble first.

MSIZE (MEMORY SIZE): “0000b” will be sent in this field. A value of “0000b” corre-

sponds to asinglebytetransfer.

Table 3. Start Fields

FWH[3:0]

Indication

1101b

FWH Memory Read

1110b

FWH Memory Write

CLK

FWH4

FWH3 - FWH0

START

IDSEL

MSIZE

28-BIT ADDRESS

AT49LW080 Datasheet(PDF) 7 Page - ATMEL Corporation

AT49LW080 Datasheet(HTML) 7 Page - ATMEL Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34

Datasheet Download

Link URL