25

AT49LW080/040

1966C–FLASH–03/02

Notes:

1. Minimum and maximum times have different loads. See PCI spec.

2. For purposes of Active/Float timing measurements, the high-Z or “off” state is defined to be when the total current delivered

through the component pin is less than or equal to the leakage current specification.

3. This parameter applies to any input type (excluding CLK).

Output Timing Parameters

Input Timing Parameters

Signal Timing Parameters

Symbol

PCI Symbol

Parameter

Min

Max

Units

t

CHQX

t

val

CLK to Data Out

(1)

211

ns

t

CHQX

t

on

CLKto Active(Float toActiveDelay)

(2)

2ns

CLK to Inactive (Active to Float Delay)

(2)

28

ns

Input Set-up Time

(3)

7ns

t

CHDX

Input Hold Time

(3)

0ns

t

VSPL

t

rst

Reset ActiveTimeafter Power Stable

1

ms

t

CSPL

t

rst-clk

Reset ActiveTimeafter CLK Stable

100

µs

Reset Active to Output Float Delay

(2)

48

ns

CLK

FWH[3:0]

(Valid Output Data)

FWH[3:0]

(Float Output Data)

CLK

FWH[3:0]

(Valid Input Data)

Inputs Valid