AT49LW080 datasheet(4/34 Pages) ATMEL

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AT49LW080/040

1966C–FLASH–03/02

CLK

INPUT

33 MHz CLOCK for FWH INTERFACE: This input is the same as the PCI

clock and adheres to the PCI specification.

A/A Mux = R/C

FWH[3:0]

I/O

FWH I/Os: I/O Communication.

A/A Mux = I/O[3:0]

FWH4

INPUT

FWH INPUT: Input Communication.

A/A Mux = WE

ID[3:0]

INPUT

IDENTIFICATION INPUTS: These four pins are part of the mechanism

that allows multiple parts to be attached to the same bus. The strapping

of these pins is used to identify the component. The boot device must

have ID[3:0] = 0000 and it is recommended that all subsequent devices

should use a sequential up-count strapping (i.e., 0001, 0010, 0011, etc.).

These pins are pulled down with internal resistors, with values between

20 and 100 k

Ω when in FWH mode. Any ID pins that are pulled high will

exhibit a leakage current of approximately 200 µA. Any pins intended to

be low may be left to float. In a single FWH system, all may be left

floating.

A/A Mux = A[3:0]

FGPI[4:0]

INPUT

FWH GENERAL PURPOSE INPUTS: These individual inputs can be

used for additional board flexibility. The state of these pins can be read

through FWH registers. These inputs should be at their desired state

before the start of the PCI clock cycle during which the read is attempted,

and should remain at the same level until the end of the read cycle. They

may

only be used for 3.3V signals. Unused FGPI pins must not be

floated.

A/A Mux = A[10:6]

TBL

INPUT

TOP SECTOR LOCK: When low, prevents programming or sector erase

to the highest addressable sector (7 in a 4-Mbit, 15 in an 8-Mbit

component) regardless of the state of the lock registers TBL high disables

hardware write protection for the top sector, though register-based

protection still applies. The status of TBL does not affect the status of

sector-locking registers.

A/A Mux = A4

INPUT

WRITE-PROTECT: When low, prevents programming or sector erase to

all but the highest addressable sectors (0 - 6 in a 4-Mbit, 0 - 14 in an

8-Mbit component), regardless of the state of the corresponding lock

registers. WP-high disables hardware write protection for these sectors,

though register-based protection still applies. The status of TBL does not

affect the status of sector-locking registers.

A/A Mux = A5

A0 - A10

INPUT

LOW-ORDER ADDRESS INPUTS: Inputs for low-order addresses during

read and write operations. Addresses are internally latched during a write

cycle. For the A/A Mux interface these addresses are latched by R/C and

share the same pins as the high-order address inputs.

Table 1. Pin Description (Continued)

Symbol

Type

Interface

Name and Function

FWH

A/A Mux

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