HMC7044 datasheet(39/72 Pages) AD

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Data Sheet

HMC7044

Rev. B | Page 39 of 72

13. Send a sync request via the SPI (set the reseed request bit)

to align the divider phases and send any initial pulse

generator stream.

14. Wait 6 SYSREF periods (6 × SYSREF Timer[11:0]) to allow

the outputs to phase appropriately (takes ~3 μs in typical

configurations).

15. Confirm that the outputs have all reached their phases by

checking that the clock outputs phases status bit = 1.

16. At this time, initialize any other devices in the system.

PLL1 may not be locked yet, but the small frequency offset

that can result on the output of the HMC7044 is not normally

severe enough to cause synchronization or initialization

failures. Configure slave JESD204B devices in the system to

operate with the SYSREF signal outputs from the HMC7044.

SYSREF channels from the HMC7044 can either be on

asynchronously, or dynamically, and can temporarily turn

on for a pulse generator stream.

17. Wait for PLL1 to lock. This takes ~50 ms for a 100 Hz BW

(from Step 11).

18. When all JESD204B slaves are powered and ready, send a

pulse generator request to send out a pulse generator chain

on any SYSREF channels programmed for pulse generator

mode.

The system is now initialized.

For power savings and the reduction of the crosscoupling of

frequencies on the HMC7044, shut down the SYSREF channels.

1. Program each JESD204B slave to ignore the SYSREF input

channel.

2. On the HMC7044, disable the individual channel enable

bits of each SYSREF channel.

To resynchronize one or more of the JESD204B slaves, use the

following procedure:

1. Set the channel enable (and SYNC enable bit) of the

SYSREF channel of interest.

2. To prevent an output channel from responding to a sync

request, disable the SYNC enable mask of each channel so

that it continues to run normally without a phase

adjustment.

3. Issue a reseed request to phase the SYSREF channel

properly with respect to the DCLK.

4. Enable the JESD204B slave sensitivity to the SYSREF

channel.

5. If the SYSREF channel is in pulse generator mode, wait at

least 20 SYSREF periods from Step 3, and issue a pulse

generator request.

POWER SUPPLY CONSIDERATIONS

The HMC7044 contains on-board regulators to shield some of

the more sensitive supplies from external noise and interference

as much as possible. Nevertheless, the user must still take

special care to the supply noise profile of the VCC1_VCO

supply to achieve the intended performance of the device.

In general, a flat input noise of 200 nV/Hz is an equivalent

contributor to the VCO noise and causes a 3 dB increase in the

noise profile from about 100 kHz to 10 MHz when the VCO is

the dominant contributor. This increase equates to a roughly

one-to-one conversion from dBV to dBc/Hz at a 1 MHz offset,

and fOUT = 2.457 GHz, that is, 200 nV/Hz = −134 dBV, and the

performance of the VCO at 1 MHz offset at 2.4576 GHz is

~−134 dBc/Hz. The PSRR of the VCO follows its closed-loop

noise profile; therefore, as the offset moves in and the VCO

profile becomes higher, the 200 nV/Hz noise stays approximately

equal to the VCO. To stay suitably below the VCO, a supply

input with <50 nV/Hz is recommended on the VCC1_VCO pin

across the 100 kHz to 10 MHz frequency range.

The output buffers are also susceptible to supply noise, but to a

lesser extent. A noise tone of −60 dBV at a 40 MHz offset results

in a −90 dBc tone at the output of the buffers in CML mode and

−85 dBc in LVPECL mode. This result is a relatively flat frequency

response, and these numbers are measured differentially. Phase

noise/spurs caused by supply noise on the output buffers do not

scale with output frequency, whereas those on the VCO do.

Table 22 lists the supply network of the HMC7044 by pin,

showing the relevant functional blocks. Six different usage

profiles are defined for the network, not including the output

channel supplies, which are accounted for separately.

The values listed under Profile 0 to Profile 5 in Table 22 and

Table 23 are the typical currents of that block or feature. If a

number is not listed in a profile column, a typical profile does

not exist for that block or feature, but the user can mix and

match features outside of the profile list, and can determine what

the power consumption is going to be given the current listings

per feature.

HMC7044 Datasheet(PDF) 39 Page - Analog Devices

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