HMC7044 datasheet(23/72 Pages) AD

23 / 72 page

Data Sheet

HMC7044

Rev. B | Page 23 of 72

THEORY OF OPERATION

The HMC7044 is a high performance, dual-loop, integer N

jitter attenuator capable of performing frequency translation,

reference selection, and generation of ultralow phase noise

references for high speed data converters with either parallel or

serial (JESD204B type) interfaces. The device is designed to

meet the requirements of demanding base station designs, and

offers a wide range of clock management and distribution

features to simplify baseband and radio card clock tree designs.

The HMC7044 uses a dual-loop architecture, where two integer

mode PLLs are connected in series to form a jitter attenuating

clock multiplier unit. The high performance dual-loop topology

of the HMC7044 enables the wireless/RF system designer to

attenuate the incoming jitter of a primary system reference

clock (for example, Common Public Radio Interface™ (CPRI)

source) and generate low phase noise, high frequency clocks to

drive data converter sample clock inputs. The HMC7044 provides

14 low noise and configurable outputs to offer flexibility in

interfacing with many different components in an RF trans-

ceiver system, such as data converters, local oscillators,

transmit/receive modules, FPGAs, and digital front-end (DFE)

ASICs.

The first PLL in the HMC7044 is designed for low bandwidth

configuration using appropriately selected external loop filter

components, and internal charge pump bias settings to achieve

less than a few hundred Hz bandwidth, typically. The exact

bandwidth roll-off points depend on the frequency spectrum of

noise that must be attenuated in the system. The first PLL locks

an external VCXO and provides the clock holdover functions

and the reference frequency to the high performance second

PLL loop. The combination of the loops provides an excellent

clock generation unit with the capability to attenuate incoming

reference clock jitter. The second PLL loop features two

overlapping on-chip VCOs that are SPI selectable with center

frequencies at 2.5 GHz and 3 GHz, respectively. Both VCOs are

designed to have wide tuning ranges for broad output frequency

coverage. The desired output frequency is set by the chosen

VCXO frequency, VCO core (higher or lower frequency core),

and the programmed second PLL feedback divider and output

channel divider values.

The HMC7044 generates up to seven DCLK and SYSREF clock

pairs per the JESD204B interface requirements. The system

designer can generate a lower number of DCLK and SYSREF

pairs, and configure the remaining output signal paths as

desired, either as DCLKs or additional SYSREFs or other

reference clocks with independent phase and frequency

adjustment. Frequency adjustment can be accomplished by

selecting the appropriate output divider values. One of the

unique features of the HMC7044 is the independent flexible

phase management of each of the 14 channels. Using a

combination of divider slip-based, digital/coarse and

analog/fine delay adjustments, each channel can be

programmed to have a different phase offset. The phase

adjustment capability allows the designer to offset board flight

time delay variations, data converter sample window matching,

and meet JESD204B synchronization challenges. The output

signal path design of the HMC7044 is implemented to ensure

both linear phase adjustment steps and minimal noise

perturbation when phase adjustment circuits are turned on.

One of the key challenges in JESD204B system design is

ensuring the synchronization of data converter frame alignment

across the system, from the FPGA or DFE to ADCs and DACs

through a large clock tree that can comprise multiple clock

generation and distribution ICs. The HMC7044 is specifically

designed to offer features to address this challenge. Using the

SYSREF valid interrupt feature, the wait time latency can be

reduced in the FPGAs. The HMC7044 raises this flag through

its GPO port when all counters are set and outputs are at the

desired phases. Additionally, an external reference-based

synchronization feature (SYNC via PLL2 or RF SYNC only in

fanout mode) synchronizes multiple devices, that is, it ensures

that all clock outputs start with same rising edge. This operation

is achieved by rephasing the SYSREF control unit deterministi-

cally, and then restarting the output dividers with this new

desired phase.

Offering excellent crosstalk, frequency isolation, and spurious

performance, the device generates independent frequencies in

both single-ended and differential formats. The four input

reference options allows up to three backup frequency sources,

with hitless switching and holdover capabilities, supporting

system redundancy and uninterrupted operation on reference

data and clock failures. The device also features dedicated

oscillator fanout mode for best clock isolation, which generates

multiple copies of the VCXO clock to be distributed across the

board with excellent frequency isolation.

Both the DCLK and SYSREF clock outputs can be configured to

support different signaling standards, including CML, LVDS,

LVPECL, and LVCMOS, and different bias conditions to offset

varying board insertion losses. The outputs can also be

programmed for ac or dc coupling and 50 Ω or 100 Ω internal

and external termination options.

The HMC7044 is programmed via a 3-wire serial port interface

(SPI) and powers up with a default configuration that generates

valid output frequencies within the VCO tuning ranges regardless

of whether a reference clock exists.

The HMC7044 is offered in a 68-lead, 10 mm ×10 mm, LFCSP

package with the exposed pad to ground.

Note that, throughout this data sheet, multifunction pins, such

as CLKIN0/RFSYNCIN, are referred to either by the entire pin

name or by a single function of the pin, for example, CLKIN0,

when only that function is relevant.

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