HMC7044 datasheet(9/72 Pages) AD

9 / 72 page

Data Sheet

HMC7044

Rev. B | Page 9 of 72

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

OPEN-LOOP VCO PHASE NOISE

fOUT = 2457.6 MHz

fOFFSET = 100 kHz

−109

dBc/Hz

High performance mode, does not include

floor contribution due to output network

fOFFSET = 800 kHz

−134

dBc/Hz

fOFFSET = 1 MHz

−136

dBc/Hz

fOFFSET = 10 MHz

−156

dBc/Hz

Normalized Phase Noise Variation vs.

Frequency

±2

Sweep across both VCOs, all bands;

normalize to 2457.6 MHz

Phase Noise Variation vs. Temperature

±2

Phase Noise Degradation in Low

Performance Mode

Guaranteed by design and characterization.

Although the device covers this range without any gaps, for frequencies between ~2700 Hz and 2900 Hz, using a different VCO core to synthesize the frequency can

be required as process parameters shift. Features are built into the HMC7044 to determine which core is selected for a given frequency that can fall in this range, but it

can require software to configure these circuits appropriately.

CLOCK OUTPUT DISTRIBUTION CHARACTERISTICS

Table 7.

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

CLOCK OUTPUT SKEW

CLKOUTx/CLKOUTx to SCLKOUTx/SCLKOUTx

Skew within One Clock Output Pair

|ps|

Same pair, same type termination and

configuration

Any CLKOUTx/CLKOUTx to Any

SCLKOUTx/SCLKOUTx

|ps|

Any pair, same type termination and configuration

CLOCK OUTPUT DIVIDER

12-Bit Divider Range

4094

1, 3, 5, and all even numbers up to 4094

SYSREF CLOCK OUTPUT DIVIDER

12-Bit Divider Range

4094

1, 3, 5 and all even numbers up to 4094; pulse

generator behavior is only supported for divide

ratios ≥ 32

CLOCK OUTPUT ANALOG FINE DELAY

Analog Fine Delay

Adjustment Range1

135

670

24 delay steps, fCLKOUT = 983.04 MHz

Resolution

fCLKOUT = 983.04 MHz (2949.12 MHz/3)

Maximum Analog Fine Delay Frequency1

3200

MHz

CLOCK OUTPUT COARSE DELAY (FLIP FLOP

BASED)

Coarse Delay Adjustment Range

½ VCO

period

17 delay steps in ½ VCO period

Coarse Delay Resolution

169.54

fVCO = 2949.12 MHz

Maximum Frequency Coarse Delay1

3200

MHz

CLOCK OUTPUT COARSE DELAY (SLIP BASED)

Coarse Delay

Adjustment Range

1 to ∞

VCO period

Resolution

339.08

fVCO = 2949.12 MHz

Maximum Frequency Coarse Delay

1600

MHz

Guaranteed by design and characterization.

HMC7044 Datasheet(PDF) 9 Page - Analog Devices

HMC7044 Datasheet(HTML) 9 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72

Datasheet Download

Link URL