HMC7044 datasheet(3/72 Pages) AD

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Data Sheet

HMC7044

Rev. B | Page 3 of 72

SPECIFICATIONS

Unless otherwise noted, fVCXO = 122.88 MHz single-ended; CLKIN0/CLKIN0, CLKIN1/CLKIN1, CLKIN2/CLKIN2, and CLKIN3/CLKIN3

differential at 122.88 MHz; fVCO = 2949.12 MHz; doubler is on; typical value is given for VCC = 3.3 V; and TA = 25°C. Minimum and maximum

values are given over the full VCC and TA (−40°C to +85°C) variation, as listed in Table 1. Note that multifunction pins, such as

CLKIN0/RFSYNCIN, are referred to either by the entire pin name or by a single function of the pin, for example, CLKIN0, when only

that function is relevant.

CONDITIONS

Table 1.

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

SUPPLY VOLTAGE, VCC

VCC1_VCO

3.135

3.3

3.465

3.3 V ± 5%, supply voltage for VCO and VCO distribution

VCC2_OUT

3.135

3.3

3.465

3.3 V ± 5%, supply voltage for Output Channel 2 and Output

Channel 3

VCC3_SYSREF

3.135

3.3

3.465

3.3 V ± 5%, supply voltage for common SYSREF divider

VCC4_OUT

3.135

3.3

3.465

3.3 V ± 5%, supply voltage for Output Channel 4, Output

Channel 5, Output Channel 6, Output Channel 7

VCC5_PLL1

3.135

3.3

3.465

3.3 V ± 5%, supply voltage for the LDO used in PLL1

VCC6_OSCOUT

3.135

3.3

3.465

3.3 V ± 5%, supply voltage for oscillator output path

VCC7_PLL2

3.135

3.3

3.465

3.3 V ± 5%, supply voltage for the LDO used in PLL2

VCC8_OUT

3.135

3.3

3.465

3.3 V ± 5%, supply voltage for Output Channel 8, Output

Channel 9, Output Channel 10, and Output Channel 11

VCC9_OUT

3.135

3.3

3.465

3.3 V ± 5%, supply voltage for Output Channel 0, Output

Channel 1, Output Channel 12, and Output Channel 13

TEMPERATURE

Ambient Temperature Range, TA

−40

+25

+85

°C

SUPPLY CURRENT

For detailed test conditions, see Table 22 and Table 23.

Table 2.

Parameter1, 2

Min

Typ

Max

Unit

Test Conditions/Comments

CURRENT CONSUMPTION3

VCC1_VCO

157

225

VCC2_OUT4

250

Typical value is given at TA = 25°C with two LVDS clocks at divide by 8

VCC3_SYSREF

VCC4_OUT4

500

Typical value is given at 25°C with two LVPECL high performance clocks,

fundamental frequency of internal VCO (fO), 2 SYSREF clocks (off)

VCC5_PLL1

125

VCC6_OSCOUT

VCC7_PLL2

VCC8_OUT4

124

500

Typical value is given at 25°C with two LVPECL high performance clocks at

divide by 2, 2 SYSREF clocks (off)

VCC9_OUT4

500

Typical value is given at 25°C with two LVDS clocks at divide by 8, 2 SYSREF

clocks (off)

Total Current

586

Maximum values are guaranteed by design and characterization.

Currents include LVPECL termination currents.

Maximum values are for all circuits enabled in their worst case power consumption mode, PVT variations, and accounting for peak current draw during temporary

synchronization events.

Typical specification applies to a normal usage profile (Profile 1 in Table 23), where PLL1 and PLL2 are locked, but very low duty cycle currents (sync events) and some

optional features are disabled. This specification assumes output configurations as described in the test conditions/comments column.

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