HMC7044 datasheet(2/72 Pages) AD

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HMC7044

Data Sheet

Rev. B | Page 2 of 72

TABLE OF CONTENTS

Features .............................................................................................. 1

Applications....................................................................................... 1

General Description ......................................................................... 1

Functional Block Diagram .............................................................. 1

Table of Contents.............................................................................. 2

Revision History ............................................................................... 2

Specifications..................................................................................... 3

Conditions..................................................................................... 3

Supply Current.............................................................................. 3

Digital Input/Output (I/O) Electrical Specifications............... 4

PLL1 Characteristics .................................................................... 5

PLL2 Characteristics .................................................................... 7

VCO Characteristics .................................................................... 8

Clock Output Distribution Characteristics............................... 9

Spur Characteristics ................................................................... 10

Noise and Jitter Characteristics ................................................ 10

Clock Output Driver Characteristics....................................... 11

Absolute Maximum Ratings.......................................................... 13

ESD Caution................................................................................ 13

Pin Configuration and Function Descriptions........................... 14

Typical Performance Characteristics ........................................... 17

Typical Application Circuits.......................................................... 21

Terminology .................................................................................... 22

Theory of Operation ...................................................................... 23

Detailed Block Diagram ............................................................ 24

Dual PLL Overview.................................................................... 25

Component Blocks—Input PLL (PLL1).................................. 25

Component Blocks—Output PLL (PLL2) .............................. 30

Clock Output Network .............................................................. 31

Reference Buffer Details............................................................ 38

Typical Programming Sequence............................................... 38

Power Supply Considerations................................................... 39

SeriaL Control Port ........................................................................ 42

Serial Port Interface (SPI) Control........................................... 42

Applications Information .............................................................. 43

PLL1 Noise Calculations ........................................................... 43

PLL2 Noise Calculations ........................................................... 43

Phase Noise Floor and Jitter...................................................... 43

Control Registers............................................................................ 44

Control Register Map ................................................................ 44

Control Register Map Bit Descriptions ................................... 52

Evaluation PCB Schematic............................................................ 69

Evaluation PCB........................................................................... 69

Outline Dimensions....................................................................... 71

Ordering Guide .......................................................................... 71

REVISION HISTORY

11/2016—Rev. A to Rev. B

Changes to Table 1 and Endnote 4, Table 2................................... 3

Changes to Reliable Signal Swing Parameter, Table 4.................. 5

Change to PLL2 VCXO Input Parameter, Table 5........................ 7

Changes to Table 7............................................................................ 9

Added Figure 13; Renumbered Sequentially .............................. 18

Added Figure 20.............................................................................. 19

Added Figure 21, Figure 22, and Figure 23................................. 20

Changes to Figure 34...................................................................... 21

Changes to Table 15 and Table 17 ................................................ 34

Changes to Figure 47...................................................................... 37

Changes to Table 23........................................................................ 41

Changes to Table 25........................................................................ 46

Changes to Table 49........................................................................ 57

Change to Table 75 ......................................................................... 68

5/2016—Rev. 0 to Rev. A

Changes to Table 3.............................................................................4

Changes to Current Range (ICP2) Parameter, Table 5....................8

Changes to Table 9.......................................................................... 11

Changes to Table 10 ....................................................................... 13

Changes to LDOBYP5 Pin Description ...................................... 15

Changes to Figure 13...................................................................... 19

Changes to Figure 30...................................................................... 25

Changes to Evaluation PCB Section ............................................ 69

Added Figure 46; Renumbered Sequentially .............................. 69

Added Figure 50 ............................................................................. 71

Updated Outline Dimensions....................................................... 71

9/2015—Revision 0: Initial Version

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