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HMC7044 Datasheet(PDF) 6 Page - Analog Devices

Part # HMC7044
Description  JESD204B clock generation
PDF  72 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

HMC7044 Datasheet(HTML) 6 Page - Analog Devices

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HMC7044
Data Sheet
Rev. B | Page 6 of 72
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
PLL1 BEHAVIOR ON REFERENCE
FAILURE1
LOS Assertion Delay7
2 + tDGPO
3 + tDGPO
tLCM
From missing signal edge to alarm on GPO
Erroneously Active ICP1 Time on
Reference Failure8
0
8
ns
Temporary Frequency Glitch Due
to Reference Failure
0.03
ppm
ICP1 = 1 mA, C12 = 4.6 nF, Crystek CVPD-952
VCXO
Integrated Frequency Error Due to
Reference Failure
0.016
ppm
ICP1 = 1 mA, C13 = 1 μF, Crystek CVPD-952 VCXO
Signal Valid Time to Clear LOS9
2
3
tLOSVAL
PLL1 VTUNE LEAKAGE SOURCES
Charge Pump Tristate Leakage
Current
0.2
nA
Board Level XTAL Tune Input Port
0.5
nA
Crystek CVPD-952 VCXO
Board Level Loop Filter
Components
2
nA
C12 = 4.6 nF, C13 = 1 μF, R9 = 11 kΩ, C15 =
unpopulated
HOLDOVER CHARACTERISTICS
VTUNE Drift Over 1 sec in Tristate
Mode
2
mV
C12 = 4.6 nF, C13 = 1 μF, R9 = 11 kΩ,
CVPD-950 VCXO
Holdover
Analog-to-Digital Converter
(ADC)/Digital-to-Analog
Converter (DAC) Resolution
19
mV
7-bit, monotonic, no missing code
ADC/DAC Code 0 Voltage
0.28
V
ADC/DAC Code 127 Voltage
2.71
V
DAC Temperature Stability
0.07
mV/°C
At maximum code
ADC/DAC Integral Nonlinearity
(INL)
−0.11
LSBs
Worst case across codes
Holdoff Timer Period1, 10
1
226
tLCM
HOLDOVER EXIT—INITIAL PHASE
OFFSETS1
Exit Criteria = Wait for Low Phase
Error
The phase offset to make up after a transition
from holdover to acquisition when using this
feature
Exit Action = None
±4
ns
Exit Criteria = Any11
Exit Action = Reset Dividers
1
2
tVCXO
Assumes N2 > 3 and dividers are reset upon
exit; note that VCXO lags at start; value applies
as the starting phase error if DAC assisted
release is used
Exit Action = None
±N1
tVCXO
Dividers are not reset upon exit
HOLDOVER EXIT CHARACTERISTICS1, 12
DAC Assisted Release Period per
Step (tDACASSIST)
1/2
1/16
tLKD
Based on lock detect timer setpoint
DAC Assisted Release Time
9
tDACASSIST
Time from decision to leave holdover until in
fully natural acquisition; assumes no
interruption by LOS or user
Delay of Exit Criteria13 = Wait for
Low Phase Error14
N1/fERR_VCXO
sec



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