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HMC7044 Datasheet(PDF) 24 Page - Analog Devices |
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HMC7044 Datasheet(HTML) 24 Page - Analog Devices |
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24 / 72 page  Data Sheet HMC7044 Rev. B | Page 24 of 72 DETAILED BLOCK DIAGRAM CLKIN0/RFSYNCIN IN0 PRESCALER (1 TO 255) RFSYNCIN/ RFSYNCIN CLKIN0/RFSYNCIN CLKIN1/FIN CLKIN1/FIN R1 DIVIDER (1 TO 65535) PHASE DETECTOR CHARGE PUMP PLL1 R2 DIVIDER (1 TO 4095) N2 DIVIDER (8 TO 4095) SYSREF TIMER LOS DETECT HOLDOVER N1 DIVIDER (1 TO 65535) 2× IN1 PRESCALER (1 TO 255) FIN/ FIN OSCIN OSCIN ANALOG DELAY CLKIN3 CLKIN3 SPI OSCOUT1 OSCOUT1 IN3 PRESCALER (1 TO 255) CPOUT1 PARTIALLY INTEGRATED LOOP FILTER INTERNAL VCO ×2 VCO1 ~ 2500MHz VCO2 ~ 3000MHz CPOUT2 FIN/FIN OSCINBUF CLK DISTRIBUTION PATH CLKOUT0 CLKOUT0 SCLKOUT1 SCLKOUT1 CLKIN2/OSCOUT0 CLKIN2/OSCOUT0 IN2 PRESCALER (1 TO 255) OSC DIVIDER ÷1, ÷2, ÷4, ÷8 DIVIDER ÷1, ÷2 2× MUX MUX MUX VCO MUX EXT VCO REF MUX PHASE DETECTOR CHARGE PUMP PLL2 SYNC/PULSOR CONTROL TO LEAF DIVIDERS COARSE DIGITAL DELAY CYCLE SLIP/ SYNC DIVIDER (1 TO 4094) FUNDAMENTAL MODE FUNDAMENTAL MODE FUNDAMENTAL MODE FUNDAMENTAL MODE FUNDAMENTAL MODE FUNDAMENTAL MODE ANALOG DELAY COARSE DIGITAL DELAY CYCLE SLIP/ SYNC DIVIDER (1 TO 4094) ANALOG DELAY CLKOUT2 CLKOUT2 SCLKOUT3 SCLKOUT3 CLKOUT8 CLKOUT8 SCLKOUT9 SCLKOUT9 MUX MUX COARSE DIGITAL DELAY CYCLE SLIP/ SYNC DIVIDER (1 TO 4094) ANALOG DELAY COARSE DIGITAL DELAY CYCLE SLIP/ SYNC DIVIDER (1 TO 4094) ANALOG DELAY SYNC GPI SPI OSCINBUF RFSYNCIN/ RFSYNCIN FSM MUX MUX ANALOG DELAY COARSE DIGITAL DELAY CYCLE SLIP/ SYNC DIVIDER (1 TO 4094) COARSE DIGITAL DELAY CYCLE SLIP/ SYNC DIVIDER (1 TO 4094) FUNDAMENTAL MODE FUNDAMENTAL MODE FUNDAMENTAL MODE FUNDAMENTAL MODE ANALOG DELAY CLKOUT4 CLKOUT4 SCLKOUT5 SCLKOUT5 CLKOUT10 CLKOUT10 SCLKOUT11 SCLKOUT11 MUX MUX COARSE DIGITAL DELAY CYCLE SLIP/ SYNC DIVIDER (1 TO 4094) ANALOG DELAY COARSE DIGITAL DELAY CYCLE SLIP/ SYNC DIVIDER (1 TO 4094) ANALOG DELAY MUX MUX ANALOG DELAY COARSE DIGITAL DELAY CYCLE SLIP/ SYNC DIVIDER (1 TO 4094) COARSE DIGITAL DELAY CYCLE SLIP/ SYNC DIVIDER (1 TO 4094) FUNDAMENTAL MODE FUNDAMENTAL MODE FUNDAMENTAL MODE FUNDAMENTAL MODE LDOs ANALOG DELAY CLKOUT6 CLKOUT6 SCLKOUT7 SCLKOUT7 CLKOUT12 CLKOUT12 SCLKOUT13 SCLKOUT13 MUX MUX COARSE DIGITAL DELAY CYCLE SLIP/ SYNC DIVIDER (1 TO 4094) ANALOG DELAY BGA BYP1 LDO BYP2 LDO BYP3 LDO BYP4 LDO BYP5 LDO BYP6 LDO BYP7 SPI SDATA SCLK SLEN ALARM GENERATION DEVICE CONTROL GPIO1 GPIO2 SYNC RESET GPIO3 GPIO4 COARSE DIGITAL DELAY CYCLE SLIP/ SYNC DIVIDER (1 TO 4094) ANALOG DELAY MUX MUX ANALOG DELAY COARSE DIGITAL DELAY CYCLE SLIP/ SYNC DIVIDER (1 TO 4094) COARSE DIGITAL DELAY CYCLE SLIP/ SYNC DIVIDER (1 TO 4094) VCXO PRESCALER (1 TO 255) Figure 35. Top Level Diagram |
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