HMC7044 datasheet(30/72 Pages) AD

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HMC7044

Data Sheet

Rev. B | Page 30 of 72

Table 14. Reference Clock Input Bit Settings

Bit Name

Description

CLKIN0/CLKIN0 In RF SYNC

Input Mode

0 = CLKIN0/CLKIN0 does not

function as an RF sync input

CLKIN1/CLKIN1 in External

VCO Input Mode

0 = CLKIN1/CLKIN1 does not

function as external VCO (FIN//FIN)

OSCOUT0/OSCOUT0

Driver Enable

1 = OSCOUT0/OSCOUT0 buffer

does not drive CLKIN2/CLKIN2 pins

Choosing fPD1

Although PLL1 supports a wide range of PFD frequencies,

there are trade-offs with setting the frequency too high or too

low. A few megahertz is high enough to allow the comparison

frequency to stay at an offset outside of the PLL2 loop BW and

thus suppress any coupling that manages to bypass the PLL1

loop filter.

Choosing fLCM

At a minimum, fLCM must be a common submultiple of all

available references. Typical frequencies include 122.88 MHz,

61.44 MHz, 38.4 MHz, 30.72 MHz, 3.84 MHz, and 1.92 MHz.

This fLCM clock is the main clock for the PLL1 digital logic. This

clock rate also scales the PLL1 lock detect timer speeds/thresholds,

holdover ADC averaging times, and LOS assertion and revalidation

delays. Higher frequencies slightly improve the response times to

reference interruptions, whereas lower frequencies can slightly

reduce current consumption of the device by up to ~10 mA.

Values in the 30 MHz to 70 MHz range are recommended.

Program the PLL1 lock detect timer threshold based on the

PLL1 loop BW and fLCM of the user.

There are reserved registers, as described in the Control Register

Map Bit Descriptions section, that must be reprogrammed from

their default values. For example, Register 0x00A5 must be set

from 0x00 to 0x06.

COMPONENT BLOCKS—OUTPUT PLL (PLL2)

PLL2 Overview

PLL2 is a very low noise integer PLL designed to multiply the

frequency from the VCXO to the VCO. It typically operates

with a loop BW of 10 kHz to 700 kHz. Use bandwidths on the

lower end of the range to preserve the inherent VCO phase

noise at 800 kHz offset (useful in GSM-based systems), where

bandwidths on the upper end can provide the best integrated

phase noise/jitter values.

Internally, PLL2 has a number of features that allow it to

efficiently achieve a Banerjee floor FOM of −232 dBc and a

flicker FOM of −266 dBc. The combination of the on-board

VCO, an internal VCXO doubler, a low N2 minimum divide

ratio, and the ability to clock the PFD at up to 250 MHz results

in an integrated jitter (at 12 kHz to 20 MHz) of 44.0 fs typical.

PLL2 has the following features:

•

Lock detect

•

Frequency doubler

•

Partially integrated loop filter

•

VCO selection, external VCO use

•

VCO calibration

•

Multichip synchronization via PLL2

Lock Detect

The lock detect function of PLL2 behaves the same way as in

PLL1. It counts the number of consecutive PFD clock cycles

that occur with a low phase error. When it reaches a count of

512, it declares lock. The threshold of 512 is adjustable, but

because the PLL2 loop BW does not vary as much as PLL1, it is

expected that the user never needs to change this threshold.

Frequency Doubler

The user can engage a frequency doubler after the VCXO buffer

and before the reference divider (see Figure 35). The frequency

doubler assumes an approximate 50% input duty cycle, where

any duty cycle distortion can result in a spur, at fPD2/2, sup-

pressed by the PLL2 loop filter. Use of the frequency doubler is

highly recommended to achieve the best spectral performance,

provided the PFD is kept under its 250 MHz frequency limit.

Partially Integrated Loop Filter

Although the large components for the PLL2 loop filter are off

chip, there is a small on-chip resister/capacitor (RC) section

formed with R = 80 Ω and C = 4.7 pF in series. This RC section

forms a higher order pole at ~420 MHz. For practical condi-

tions, this filter segment does not affect the stability of the loop.

OFF-CHIP

VCO

4.7pF

80Ω

Figure 42. On-Chip RC Circuit

Figure 43 shows the VCO input network. Depending on the

frequency band of interest (2.5 GHz or 3.0 GHz), the user must

specify which VCO to enable via the VCO Selection[1:0] SPI

word. To use the CLKIN1/FIN pin as an external VCO signal,

program this word to 0, and set the CLKIN1/CLKIN1 in external

VCO input mode bit.

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