HMC7044 datasheet(27/72 Pages) AD

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Data Sheet

HMC7044

Rev. B | Page 27 of 72

INIT

RESET

PRELOAD

LOCKING

LOCKDET

LOS ACTIVE REF

NOT LOCKDET

AT LEAST ONE REFERENCE OK AND BEST

AVAILABLE REFERENCE IS SELECTED

[AND PHASES CROSSED ZERO (OPTIONAL)]

[AND DAC ASSISTED RELEASE COMPLETE (OPTIONAL)]

JUST ENTERED HOLDOVER (<HOLDOFF TIMER[7:0])

AND PREVIOUS CLOCK RECOVERS

[AND DAC ASSISTED RELEASE COMPLETE (OPTIONAL)]

REVERTIVE

AND HIGHER PRIORITY

CLOCK IS AVAILABLE

LOCKED

HOLDOVER

Figure 37. PLL1 FSM Simplified State Diagram—

Autorevertive Reference Switching = 1

PLL1 Reference Inputs

PLL1 accepts up to four candidate references on CLKIN3/CLKIN3

to CLKIN0/CLKIN0. If all references appear valid, according to

the LOS, PLL1 uses a reference priority table to select the best

candidate. Using the PLL1 reference priority control bits, program

the highest priority clock (CLKIN0/CLKIN0, CLKIN1/CLKIN2,

CLKIN2/CLKIN2, or CLKIN3/CLKIN3), and then second

priority clock, and so on. It is not necessary to include unused

reference inputs in the reference priority table. Instead, specify

the same useful clock in multiple positions. In automode, reference

switching occurs in the preload state (see Figure 37) as PLL1

exits reset, or while PLL1 is in the holdover state.

The reference clock input pins (Pin 36, Pin 37, Pin 39, Pin 40,

Pin 42, and Pin 43) have dual functions; therefore, SPI configura-

tion is important for proper functionality. See the PLL1

Programming Considerations section for more information

about the relevant control bits, and the Reference Buffer Details

section for interface recommendations.

When a reference fails, the sourcing circuit recognizes a fault

and disables either the clock or the buffer driving the signal to

the HMC7044. For this reason, hysteresis in the input buffers

prevents internal toggling for signal swings <~75 mV p-p

differential, which allows further elements in the PLL1 architecture

to cleanly recognize the interruption and prevent unwanted

transients in the frequency.

PLL1 LOS Detection

The HMC7044 checks the validity of a reference by comparing

its approximate frequency vs. the VCXO. The HMC7044 supports

references at different frequencies. The first step is to divide the

available references and the VCXO to the lowest common multiple

frequency (fLCM). These divider settings are available via the SPI

control bits (CLKINx/CLKINx Input Prescaler[7:0] and OSCIN/

OSCIN Input Prescaler[7:0]). In the example shown in Figure 36,

fLCM = 61.44 MHz. The VCXO derived clock at fLCM is the main

clock to the PLL1 FSM controlling the FSM, lock detect timer,

and ADC/DAC filtering and holdover circuits. Although not

required, using the VCXO clock allows the LOS detection and

PLL1 FSM to operate at a higher rate than the PFD, allowing it to

recognize a reference failure early and enter holdover, sometimes

before a failing reference that has started to drift in either phase

or frequency (or both) can influence the PFD or CP.

The dividers in the LOS block, and to some extent, R1, pose a

few challenges. The input frequencies are up to 800 MHz, with a

wide divider range. Furthermore, they are designed to tolerate

glitchy clocks without catastrophic results, because a reset phase

is not always available after an issue is detected.

When all the references are divided to the same frequency, they

are compared relative to the VCXO derived path, and thus each

other. This comparison is performed by a circuit that looks for

three edges of a clock within one period of the other. If it appears

that a reference signal is too slow, its LOS flag is asserted and, in

automode, PLL1 uses this information to disqualify and/or

abandon a reference. Conversely, if it appears that the VCXO is

too slow according to any of the active references, a warning is

generated (available as one of the configurable options for the

GPO, or readable on the SPI) but no automated action occurs.

The HMC7044 monitors reference signals for three edges of a clock

within one period of the other, instead of the more intuitive two

edges, to avoid false LOS flags as clocks that are slightly out of

frequency cross each other in phase in the presence of interference,

noise, and circuit offsets. The result is that the LOS triggers when

the failing reference clock frequency is approximately an octave

from the intended frequency.

After a reference signal returns and its frequency is within an

octave of the VCXO, two to three cycles of the LOS validation

timer must expire before the LOS flag is deasserted and the

reference is considered for potential use. The LOS validation

timer is programmable between 0 LCM cycles (no hysteresis),

and 64 LCM cycles via LOS Validation Timer[2:0] in

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