AL300 datasheet(39/64 Pages) ETC

39 / 64 page

AL300

November 28, 2001

YUV Video horizontal capture start is defined by register #20h and

#21h. Note that when #20h values changes between odd and even, the

output U/V may flip. #20h should stay either odd or even at all times

to ensure correct U/V.

When SoftTVRef is 0, register#20h<0> will be used as U/V Flip

The counterpart for controlling graphic reference is defined by SoftGraRef

(register #80h<6>)

Interpolation

<7>

turn on interpolation

turn off interpolation (duplicate pixels only)

07h:

Adjustment (R/W) [ADJUSTMENT]

Reserved

<7>

HDEDelay

<6:4> PDSPEN delay relative to output data phase

Reserved

<3:0>

Optimized value is 00h for single pixel mode, 20h for dual pixel mode

Please also program registers #05h<5>, #43h<7>, and #43h<4> accordingly for dual pixel mode.

Output Clock PLL and Zoom Ratio:

The output pixel clock is generated from the input HSYNC (or with input pixel clock) relative to the ratio

between the output and input display resolution. The PLL divider (PLLDIV, defined by registers #10h and

11h) has a maximum value of 2047 programmed by an 11-bit word. PLLDIV is defined by the following

equation:

For the best scaling quality, PLLREFDIV (defined by registers #12h and #13h) is used as a PLL reference

divider. In this case, PLLREFDIV (M) should be equal to the total number of pixels per input line (Hi). If

N is greater than 2047, both N and M need to be adjusted by dividing the scaling ratio by a simple integer

as in the following example:

Example: (N greater than 2047)

PLLDIV(N) =

Where, Ho is the total number of pixels per output line

Vo is the output active lines per frame

Vi is the input active lines per frame

AL300 Datasheet(PDF) 39 Page - List of Unclassifed Manufacturers