AL300 datasheet(9/64 Pages) ETC

9 / 64 page

AL300

November 28, 2001

For AL300 ver. A, the B data lag A data by 90

° (half

SCLK).

For AL300 ver. B, A and B data are aligned.

BB<7:0>

OUT (CMOS) 72-75, 77-80

Right Pixel of Interleaved Blue Output in Dual Pixel

Mode

Valid when Register 0x43 bit4 = ‘1’.

Data are output with PCLKB.

For AL300 ver. A, the B data lag A data by 90

° (half

SCLK).

For AL300 ver. B, A and B data are aligned.

PCLKA

OUT (CMOS) 84

Leading Pixel Clock of Interleaved Video Output for

Right data in Dual Pixel Mode. Polarity is

programmable

PCLKB

OUT (CMOS) 85

Lagging Pixel Clock of Interleaved Video Output for

Right data in Dual Pixel Mode. Polarity is

programmable.

Default PCLKB lags PCLKA by 180

° (one SCLK).

SCLK

OUT (CMOS) 86

Display Pixel Clock (for single pixel per clock mode)

PHS

OUT (CMOS) 88

Panel/Display Hsync

Can be programmed to either polarity.

PVS

OUT (CMOS) 89

Panel/Display Vsync

Can be programmed to either polarity.

PDSPEN

OUT (CMOS) 90

Panel/Display Display Enable; used to indicate active

output pixels (HDE).

Can be programmed to either polarity.

RA<7:0>

OUT (CMOS) 92-95, 97-100 Red Data Output

When Register 0x43 bit4 = ‘0’, data are output every

SCLK.

When Register 0x43 bit4 = ‘1’, the left pixel of

interleaved red data are output with PCLKA.

GA<7:0>

OUT (CMOS) 102-105, 107-

110

Green Data Output

When Register 0x43 bit4 = ‘0’, data are output every

SCLK.

When Register 0x43 bit4 = ‘1’, the left pixel of

interleaved red data are output with PCLKA.

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