AL300 datasheet(10/64 Pages) ETC

10 / 64 page

AL300

November 28, 2001

BA<7:0>

OUT (CMOS) 112-115, 117-

120

Blue Data Output

When Register 0x43 bit4 = ‘0’, data are output every

SCLK.

When Register 0x43 bit4 = ‘1’, the left pixel of

interleaved red data are output with PCLKA.

PLL (Phase Lock Loop) Interface

IHSREF

OUT (CMOS) 123

Input Hsync Reference, buffered and polarity adjusted,

usually for input PLL to regenerate input pixel clock.

Always positive polarity.

When no input HSYNC is present, virtual IHSREF

can be generated by programming registers 41h & 42h

OHSREF

OUT (CMOS) 124

Output Hsync Reference, for output PLL to generate

output pixel clock.

Always positive polarity.

OHSREF is either equivalent to IHSREF or the

equally divided IHSREF. Refer to registers 03h,

10h~13h.

OHSFB

OUT (CMOS) 125

Output PLL Feedback; works with OHSREF to

generate output pixel clock

OCLK

IN (CMOSd)

126

Output Clock, connected to OPLLCLK when internal

PLL is used; connected to external PLL clock output

when external PLL is used

OPLLCLK

OUT (CMOS) 127

Recovered Output Clock generated by the internal PLL

VCOIN

129

PLL External VCO Filter Circuit Input

OSD ROM Interface

ROMDATA

<7:0>

IN (CMOSd)

132-135, 137-

140

OSD ROM Data

ROMADDR

<15:0>

OUT (CMOS) 160-157, 155-

152, 150-147,

145-142

OSD ROM Address

Power, Ground, Reset

RESETB

IN (CMOS)

122

Reset, active low

PLLVCC

POWER

128

VCC of Internal PLL, 3.3V

PLLGND

GROUND

130

GND of Internal PLL

VCC

POWER

19, 37, 51, 61, Digital VCC, 3.3V

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