AL300 datasheet(8/64 Pages) ETC

8 / 64 page

AL300

November 28, 2001

IREQ

OUT (CMOS) 41

Interrupt Request, active high

SCL

IN (CMOSs)

I2C Serial Clock Input

SDA

INOUT

(COMSsu)

I2C Serial Data Input/Output

GOUT1

OUT (CMOS) 81

General Purpose Output

Connected to Register 0x1B bit 2

GOUT2

OUT (CMOS) 82

General Purpose Output

Connected to Register 0x1B bit 3

GOUT3

OUT (CMOS) 83

General Purpose Output

Connected to Register 0x1B bit 1

Configuration

PWRDN

IN (CMOSd)

Power Down

0, Normal Operation

1, Power Down

I2CADDR

IN (CMOSd)

I2C Bus Slave Address Select

0, write address = 70, read address = 71

1, write address = 72, read address = 73

YUVIN

IN (CMOSd)

YUV Input

0, RGB Format Video Input

1, CCIR YUV Format Video Input

Refer to RIN, GIN, BIN pins

Test1

IN (CMOSd)

Test Pin

Test2

IN (CMOSd)

Test Pin

Panel/Display Interface

RB<7:0>

OUT (CMOS) 52-55, 57-60

Right Pixel of Interleaved Red Output in Dual Pixel

Mode

Valid when Register 0x43 bit4 = ‘1’.

Data are output with PCLKB.

For AL300 ver. A, the B data lag A data by 90

° (half

SCLK).

For AL300 ver. B, A and B data are aligned.

GB<7:0>

OUT (CMOS) 62-65, 67-70

Right Pixel of Interleaved Green Output in Dual Pixel

Mode

Valid when Register 0x43 bit4 = ‘1’.

Data are output with PCLKB.

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