AL300 datasheet(16/64 Pages) ETC

16 / 64 page

AL300

November 28, 2001

The AL300’s internal PLL has better performance at high frequency than low frequency when the

output rate is within 110MHz.

To take advantage of this property, there are four “divide-by-2”

dividers for optimal operation. The FEB1 and FEB2 work as frequency multipliers; the PRE and

OUT work as frequency dividers.

To turn on or off these dividers, control register #11h. The

recommended values for the register setting at different input modes are as follows:

Ref freq.

(KHz)

Fout

(MHz)

Divider

value

FEB2 FEB1 OUT PRE

DIVIDER

Reg. 11h

(Hex)

Reg. 10h

(Hex)

31.5

25.2

800

011,00011110

37.5

31.5

840

011,01000110

37.88

1056

010,00001110

46.75

49.368

1056

010,00001110

48.0

64.8

1350

010,10100001

56.5

74.92

1326

010,10010101

60.0

78.72

1312

010,10001110

85.5

1336

010,10011010

107.52

1680

011,01000110

The output pixel clock can be either from the internal PLL locked to the ref_in clock, or from the

external clock pin, OCLK.

The ref_in reference clock is the GHS, TVHS, or the pseudo-reference

clock generated by the PLLREFDIV.

The frequency of the reference clock ref_in is between 10 KHz and 1 MHz. The output frequency is

adjustable and the maximum frequency is up to 110 MHz. Details about the PLL related registers can

be found in the Register Definition section.

OPLLCLK

CLOCK

OUTPUT

FEB2

FEB1

DIVIDER

OUT

BUFFER

REF IN

(GHS, TVHS, or the

ref. generated by M )

PRE

PHASE

DETECTOR

CHARGE

PUMP

VCO

DIVIDER

VCOIN

( LOOP FILTER )

AL300-29 Internal PLL Block Diagram

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