IR3092

Page 10 of 37

06/25/04

IR3092 THEORY OF OPERATION

7.8V START

7.3V STOP

45U

ON

VCCL

FAST DAC

18uA

5.5U

4.9V

BB DISABLE COMPARATOR

80mV

IOVP

ON

45k

1.9us

BLANKING

0.7V

BIASOUT

SS

ROSC

OVP

Error_Amp

CSINM

RSFF

S

Q

QB

R

CSINP1

SCOMP

VCCH1

5VUVL

GATEL2

VID2

GateHI

GATEHI

OL_OUT

OL_IN

IN

IROSC

summer

ENABLE

+

-

Share Adjust Error Amp

55U

OVER CURRENT

VID5

-

+

EQUAL DUTY CY CLE COMPARATOR

IROSC

-

+

X25

GATEHI1

VID1

VCC

OVP Comparator

X25

PGND1

VOSNS-

0.7V

-

+

DELAY

0 TO IROSC*3/4

GATEH2

OCSET

IROSC

FAULT LATCH

S

R

VDRP

VID4

0% DUTY CYCLE

summer

+

-

IROSC

DAC BUFFER

4V

1.243

0.55V

240mV chrg, 210mV dischrg

PGND2

U18

-

+

Discharge Comparator

GATEL1

FB

RSFF

S

Q

QB

R

SETBIAS

EAOUT

-

+

UVL

LGND

VCCL

10p

10p

GateLO

GATELO

OL_IN

IN

OL_OUT

GateHI

GATEHI

OL_OUT

OL_IN

IN

4 X IROSC

GateLO

GATELO

OL_IN

IN

OL_OUT

CSINP2

+

-

1.3V

Sof tStart_Clamp

SET DOMINANT

RESET DOMINANT

RESET DOMINANT

-

+

VID0

PWRGD

VDAC

CLK1

CLK2

IROSC

Oscillator

PWM COMPARATOR

60K

0.7V

IROSC/2

PWM COMPARATOR

VID3

0.26V

IROSC

DAC

OUT

F11111

OPTERON_DAC

ATHLON_DAC

VDAC

FB

15k

3V

OFF

DAC DEFAULTS TO VR10

WITH VID_SEL GROUNDED

DISABLE

VCCH2

AMD=1.5V

INTEL=0.6V

VOSNS-

110K

1

-

+

UVL

3.3V

5V

AMD=450mV

INTEL=150mV

VID_SEL

4.300V START

4.125V STOP

1.2V

3.4V

VDAC

VDAC

H FORCES IROSC/2 AT SS<0.7V

Figure 1 – IR3092 Block Diagram

PWM Operation

The IR3092 is a fully integrated 2 phase interleaved PWM control IC which uses voltage mode control with trailing edge

modulation. A high-gain wide-bandwidth voltage type Error Amplifier in the control IC is used for the voltage control loop.

The PWM block diagram of the IR3092 is shown in Figure 2.

Refer to Figure 3. Upon receiving a clock pulse, the RSFF is set, the internal PWM ramp voltage begins to increase, the

low side driver is turned off, and the high side driver is then turned on. For phase 1, an internal 10pf capacitor is charged

by a current source that’s proportional to the switching frequency resulting in a ramp rate of 57mV per percent duty cycle.

For example, if the steady-state operating switch node duty cycle is 10%, then the internal ramp amplitude is typically

570mV from the starting point (or floor) to the crossing of the EAOUT control voltage. When the PWM ramp voltage

exceeds the Error Amplifier’s output voltage, the RSFF is reset. This turns off the high side driver, turns on the low side

driver, and discharges the PWM ramp to 0.7V until the next clock pulse.