IR3092

Page 11 of 37

06/25/04

CSINM

CLK1

CLK2

IROSC

U39

OSCBLOCK

10p

10p

RESET DOMINANT

ROSC

ROSC

VDRP BUFFER

RESET DOMINANT

-

+

BB DISABLE

80mV

0.55V

IROSC

-

+

PWM COMPARATOR

0 TO IROSC*3/4

+

-

Share Adjust Error Amp

IROSC

ERROR AMPLIFIER

0.7V

RCS2

RSFF

S

QB

R

CSC2

IROSC/2

CCS1

1

2

CCS2

-

+

PWM COMPARATOR

RSC2

RCS1

CCOMP

CDAC

VDAC

RFB

0% DUTY CY CLE

RSFF

S

QB

R

CLK2

RDRP

RCOMP

RDAC

0.7V

COUT

1

2

VDAC

EAOUT

SCOMP

VDRP

GATEH2

GATEL1

GATEH1

CSINP1

GATEL2

VOSNS-

CSINP2

FB

VOUT SENSE+

VOUT+

VOUT SENSE-

VOUT-

VIN

VIN

VDAC

-

+

X24.5

VDAC

-

+

X24.5

CLK2

Figure 2 – PWM Block Diagram

The RSFF is reset dominant allowing both phases to go to zero duty cycle within a few tens of nanoseconds in response

to a load step decrease. Phases can overlap and go to 100% duty cycle in response to a load step increase with turn-on

gated by the clock pulses. An Error Amplifier output voltage greater than the common mode input range of the PWM

comparator results in 100% duty cycle regardless of the voltage of the PWM ramp. This arrangement guarantees the

Error Amplifier is always in control and can demand 0 to 100% duty cycle as required. It also favors response to a load

step decrease which is appropriate given the low output to input voltage ratio of most systems. The inductor current will

increase much more rapidly than decrease in response to load transients.

This control method is designed to provide “single cycle transient response” where the inductor current changes in

response to load transients within a single switching cycle maximizing the effectiveness of the power train and minimizing

the output capacitor requirements.