IRCC datasheet(27/79 Pages) SMSC

27 / 79 page

the Line Control/Status registers, and the Bus

Status register (Table 15).

Typically, the controls in Register Block Zero are

used during IrDA FIR and Consumer IR

message transactions.

Table 15 - Register Block Zero

Address

Directio

Description

Default

R/W

Data Register

Interrupt Identification Register

'00'hex

active

frame

eom

raw

mode

fifo

R/W

Interrupt Enable Register

'00'hex

active

frame

eom

raw

mode

fifo

Line Status Register (read)

'00'hex

under-

run

over

run

frame

error

size

error

crc

error

frame

abort

Line Status Address Register (write)

status register

address

R/W

Line Control Register A

'00'hex

fifo

reset

fast

g. p.

data

raw

abort

data

done

R/W

Line Control Register B

'00'hex

sce modes

bits

sip

enable

brick

wall

message

count

Bus Status Register

'00'hex

not

empty

fifo

full

time-

out

Data Register (Address 0)

The Data Register is the FIFO access port.

Typically, the user will only write to the FIFO

when transmitting and read from the FIFO when

receiving. The Host always has read access to

the FIFO regardless of the state of the SCE

Modes bits or the Loopback bit.

Host read

access to the FIFO is blocked when the FIFO is

empty. The Host has write access to the FIFO

only when the Loopback bit is inactive and the

SCE Modes bits are zero or Transmit mode is

enabled.

Host write access to the FIFO is

blocked when the FIFO is full.

Interrupt Identification Register (Address 1)

Active Frame, bit 7

When this bit is one, an Active Frame has

occurred (see the Active Frame Indicator

section). The Active Frame typically indicates

that the SCE receiver has detected a valid

incoming IrDA FIR or TV Remote start-of-frame

sequence.

Reading the Interrupt Identification

IRCC Datasheet(PDF) 27 Page - SMSC Corporation

IRCC Datasheet(HTML) 27 Page - SMSC Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79

Datasheet Download

Link URL