IRCC datasheet(28/79 Pages) SMSC

28 / 79 page

EOM, bit 6

When this bit is one, an End of Message has

occurred. The EOM indicates the end of an IrDA

FIR EOF or Abort.

During Consumer IR

messages EOM also indicates FIFO underruns/

overruns and DMA Terminal Counts. Reading

the Interrupt Identification register resets the

EOM bit.

Raw Mode Interrupt, bit 5

When this bit is one, a Raw Mode interrupt has

occurred. The Raw Mode Interrupt indicates that

the Raw Rx Control bit has gone active. Reading

the Interrupt Identification register resets the Raw

Mode Interrupt bit.

FIFO Interrupt, bit 4

When this bit is one, a FIFO Interrupt has

occurred. The FIFO Interrupt indicates that the

FIFO Interrupt Enable is active and either a

TxServReq or an RxServReq has occurred. The

FIFO Interrupt bit is cleared when the interrupt is

disabled; i.e., reading the Interrupt Identification

Interrupt Enable Register (Address 2)

Setting any of the bits in this register to one

enables the associated interrupt (see the

Interrupt

Identification

onto

the

Interrupt Request (IRQ) line defined in the

Interface Description. Interrupts will only occur if

both the interrupt enable bit and the Master

Interrupt Enable bit (see the Master Block

Control Register) are active.

The interrupt enables do not affect the bits in the

Interrupt ID (IID) register, except for the FIFO

Interrupt. For example, a Raw Mode interrupt

that occurs while the Raw Mode Interrupt Enable

is inactive will alter the Raw Mode Interrupt

indicator in the IID register but will not activate

the IRQ line. Toggling the FIFO Interrupt Enable

will affect the FIFO Interrupt indicator in the IID

Line Status Register(s) (Address 3)

Error Indicators (read-only)

There are eight Line Status Registers at address

3. Each register is read-only and is accessed

using the three Status Register Address bits,

also located at this address.

The FIFO

Underrun, FIFO Overrun, Frame Error, Size

Error, Frame Abort, and CRC Error flags indicate

the status of any one of eight IrDA FIR message

frames. The Error Indicators, in all registers, are

reset following a Master Reset, Power-On-Reset,

and Error Reset (see the Master Block Control

status register only (see the Message Count bits)

are reset following a valid IrDA BOF sequence.

FIFO Underrun, bit 7

The FIFO Underrun bit gets set to one when the

IrDA FIR transmitter runs out of FIFO data and

the Data Done bit is not active.

FIFO Overrun, bit 6

The FIFO Overrun bit gets set to one when the

IrDA FIR receiver tries to write data to the FIFO

when the FIFO Full flag is active.

Frame Error, bit 5

The Frame Error bit gets set to one when IrDA

framing errors are detected; for example, HDLC

pulse-widths greater than one bit-cell, and invalid

framing fields (see the section Framing Errors).

Size Error, bit 4

The Size Error bit is set to one whenever the

IrDA FIR receiver decrements the Rx Data Size

count to zero before the End-Of-Frame, or

whenever the the Brick Wall bit is inactive and

the IrDA FIR transmitter decrements the Tx Data

Size count to zero before FIFO Empty goes

active.

IRCC Datasheet(PDF) 28 Page - SMSC Corporation

IRCC Datasheet(HTML) 28 Page - SMSC Corporation

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