IRCC datasheet(69/79 Pages) SMSC

69 / 79 page

Burst Mode Transmit

Uses FIFO Threshold for Triggered Transmit.

The IrDA 4PPM transmit encoder can deplete

the SCE FIFO faster than an ISA Host can fill it.

The FIFO Threshold can be used to allow the

DMA controller to load enough data into the

FIFO

before

transmission

begins

accommodate system latencies for subsequent

DMA transfer cycles.

The FIFO Threshold is

otherwise not used for DMA transfers.

DRQ Control

In DMA Burst Mode, DRQ remains active until

the entire DMA data block has been transferred,

as indicated by DMA Terminal Count (TC). The

internal FIFO Full signal can temporarily

deactivate DRQ if the DMA block has not been

completely transferred but there is no room left in

the FIFO for more data. As soon as the FIFO

Full becomes inactive, DRQ is reasserted. The

internal

Refresh

Interval

signal

can

also

temporarily deactivate DRQ (see the 32 I/Ox

Clock DMA Refresh Counter).

Example: Transmit a 256-Byte IrDA Message

Setup and enable the DMA controller for the

256-byte message.

Set

the

appropriate

FIFO

Threshold,

typically this number can be high, e.g. 127,

and set the SCE Modes bits in Register

Block Zero, Address 6 to enable the

transmitter.

The DMA controller proceeds to load the

FIFO

until

TxServReq

activates

the

transmitter. DMA transfer cycles continue

until TC.

DRQ is only de-asserted when

FIFO Full or Refresh Interval are active

(Figure 39).

DMA Enable

DRQ

I/Ox

nDACK

Refresh Interval

32 clocks

max.

350ns

min.

Disable 32-Clk

Countdown & Reset

32-Clk Counter

Enable 32-Clk

Countdown

DMA Burst

FIGURE 38 - 32 I/OX CLOCK DMA REFRESH COUNT TIMING

IRCC Datasheet(PDF) 69 Page - SMSC Corporation

IRCC Datasheet(HTML) 69 Page - SMSC Corporation

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