IRCC datasheet(35/79 Pages) SMSC

35 / 79 page

No Wait, bit 3

When the No Wait bit is one, the ISA Bus

nSRDY signal goes active following the trailing

edge of the ISA I/O command and inactive

following the rising edge (see Zero Wait State

Support).

String Move, Bit 2

When the String Move bit is one, the

programmed I/O host interface is qualified by

IOCHRDY (Table 23). See IOCHRDY Time-Out.

DMA Burst Mode, bit 1

When the DMA Burst Mode bit is one, DMA

Burst (Demand) mode is enabled.

When the

DMA Burst Mode bit is zero, Single Byte DMA

mode is enabled (Table 23).

DMA Enable, bit 0

DMA Enable is connected to a signal in the

Interface Description called DMAEN that is used

by the chip-level interface to tristate the IrCC

DMA controls when the DMA interface is

inactive. When the DMA Enable bit is one, the

DMA host interface is active (Table 23). When

the DMA Enable bit is zero (default), the nDACK

and TC inputs are disabled and DRQ output is

gated off.

Table 23 - I/O Interface Modes

STRING

MOVE

DMA

BURST

DMA

ENABLE

FUNCTION

Programmed I/O, no IOCHRDY

Programmed I/O, uses IOCHRDY

Single Byte DMA Mode

Demand Mode DMA

FIFO Threshold Register (Address 2)

The FIFO Threshold Register contains the

programmable FIFO threshold count. The FIFO

Threshold is programmable from 0 to 127. Bit 7

in the FIFO Threshold register is read-only and

will always return zero. FIFO Threshold values

typically reflect the overall I/O performance

characteristics of the host; the lower the value,

the longer the interval between service requests

and the faster the host must be to successfully

service them. The same threshold value can be

used for both I/O read and I/O write cases.

IRCC Datasheet(PDF) 35 Page - SMSC Corporation

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