IRCC datasheet(33/79 Pages) SMSC

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Table 19 - IrCC Logical Block Controls

MODE

DESCRIPTION

COM

16550 UART COM Port (default)

IrDA SIR - A

Up to 115.2Kbps, Variable 3/16 Pulse

ASK IR

Amplitude Shift Keyed Ir Interface

IrDA SIR - B

Up to 115.2Kbps, Fixed 1.6us Pulse

IrDA HDLC

Includes.576Mbps & 1.152Mbps

IrDA4PPM

Includes 4Mbps

CONSUMER

TV Remote

RAW IR

Direct IR Diode Control

OTHER

Reserved

Half Duplex, bit 2

When Half Duplex is zero (default), the 16550A

is in full duplex mode. The Half Duplex bit only

supports the 16550A UART; i.e., this bit has no

effect on the IrCC SCE. The Half Duplex bit is

analogous to the chip-level configuration register

Half Duplex bit and has the same affect on the

UART. Provisions must be made in legacy

devices to accommodate Half Duplex selection

through

either

the

chip-level

configuration

registers or the IrCC Half Duplex bit; i.e., the last

write from either source determines the current

mode selection and is visible in both registers.

Tx/Rx Polarity Bits, 0 - 1

The Tx and Rx Polarity bits define the active

states for signals entering and exiting the Output

Multiplexer ports. IrCC Active states are typically

decoded as zero. The Tx Polarity bit default is

one; the Rx Polarity bit default is zero.

For backward compatibility, the Tx and Rx

Polarity bits do not apply to COM mode; i.e.,

when the Block Control bits are zero.

The

relationship between the Output Multiplexer port

signals and the Polarity bits is an exclusive-or

(Table 20). For example, if the IRRx pin in the

Output Multiplexer is one and the Rx Polarity bit

is zero, the signal is inactive and therefore

decoded as a one. The IrCC Tx Polarity bit (bit

1) is equivalent to the Transmit Polarity bit in the

chip-level configuration space of earlier devices;

e.g., the FDC37C93X IR Option Register, Serial

Port 2, Logical Device 5, Register 0xF1. The Rx

Polarity bit (bit 0) is equivalent to the Receive

Polarity bit in the same register. Provisions have

been made in legacy devices to accommodate

Polarity bit selection through either the chip-level

configuration registers or the SCE registers; i.e.,

the last write from either source determines the

current Polarity bit value and is visible in both

registers.

Table 20 - Tx/Rx Polarity Bit Effects

SIGNAL

POLARITY BIT

DECODED SIGNAL

IRCC Datasheet(PDF) 33 Page - SMSC Corporation

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