IRCC datasheet(70/79 Pages) SMSC

70 / 79 page

Burst Mode Receive

DRQ Control

In DMA Burst Mode, DRQ remains active until

the entire DMA data block has been transferred,

as indicated by DMA Terminal Count (TC).

Since the FIFO Threshold is not used for DMA

transfer cycles, DRQ is asserted as soon as

FIFO Not Empty is true.

FIFO Not Empty can

temporarily deactivate DRQ if the DMA block has

not been completely transferred but there is no

data left in the FIFO to transfer. As soon as

FIFO Not Empty becomes true, DRQ is

reasserted. The internal Refresh Interval signal

can also temporarily deactivate DRQ (see the 32

I/Ox Clock DMA Refresh Counter).

Example: Receive a 256-Byte IrDA Message

Setup and enable the DMA controller for the

256-byte message.

Enable the IrDA Receiver.

DRQ is asserted as soon as FIFO Not

Empty is true.

The DMA controller proceeds to empty the

FIFO until TC. DRQ is otherwise only de-

asserted when FIFO Not Empty is false or

Refresh Interval is active (Figure 40).

DM A E n a b le

DR Q

FIFO F U L L

DM A Bu rs t

R e fresh In te rv al

T x E n a b le

Tx S e rv Re q

FIGURE 39 - DMA BURST MODE TRANSMIT TIMING

DM A E n ab le

DR Q

FIFO NO T E M PT Y

DM A Bu rst

R efresh In terv al

Rx E n ab le

FIGURE 40 - DMA BURST MODE RECEIVE TIMING

IRCC Datasheet(PDF) 70 Page - SMSC Corporation