IRCC datasheet(6/79 Pages) SMSC

6 / 79 page

Table 6 - SYSTEM Signals

NAME

SIZE (BITS)

TYPE

DESCRIPTION

CLK

Input

System Clock

RESET

Input

IrCC System Reset

Power Down

Input

Low Power Control

DMAEN

Output

DRQ Tristate Control

IRQEN

Output

IRQ Tristate Control

nACE

Input

ACE 550 Register Bank Select

nSCE

Input

SCE Register Bank Select

VCC

Power

System Supply

GND

Power

System Ground

DMAEN

DMAEN is used by the chip-level interface to

tristate the IrCC DRQ output when the DMA

Enable bit is inactive. The DMA Enable bit is

located in SCE Configuration Register B, bit 0.

IRQEN

IRQEN is used by the chip-level interface to

tristate the IrCC IRQ output when the OUT2 bit is

inactive.

The OUT2 bit is located in 16550A

MODEM Control Register.

Power Down

The Power Down pin is used by the chip-level

interface to put the SCE into low power mode.

NOTE: Power Down does not force the ACE550

into low power mode.

CHIP-LEVEL CONFIGURATION CONTROLS

The following signals come from chip-level

configuration registers. There are two types of

Chip-Level Configuration Controls: IrCC-Specific

controls, and Legacy Controls. Both types have

equivalent controls in either the IrCC ACE or

SCE Registers.

The IrCC-Specific controls have been newly

added primarily to support the IrCC block.

Provisions have been made in new chip-level

configuraton contexts to accommodate these

signals.

The Legacy controls already exist in other

contexts. Provisions have been made in legacy

devices to accommodate these controls from

either the Chip-Level Configuration Registers or

the IrCC Registers; i.e., the last updated value

from either source determines the current control

state and is visible in both registers.

IRCC Datasheet(PDF) 6 Page - SMSC Corporation

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