IRCC datasheet(44/79 Pages) SMSC

44 / 79 page

LINE CONTROL REGISTER (LCR)

Address Offset = 3H, DLAB = 0, READ/WRITE

This register contains the format information of the

serial line. The bit definitions are:

Bits 0 and 1

These two bits specify the number of bits in each

transmitted or received serial character.

The

encoding of bits 0 and 1 is as follows:

BIT 1

BIT 0

WORD LENGTH

5 Bits

6 Bits

7 Bits

8 Bits

The Start, Stop and Parity bits are not included in

the word length.

Bit 2

This bit specifies the number of stop bits in each

transmitted or received serial character.

The

following table summarizes the information.

BIT 2

WORD LENGTH

NUMBER OF

STOP BITS

5 bits

1.5

6 bits

7 bits

8 bits

Note: The receiver will ignore all stop bits beyond

the first, regardless of the number used in

transmitting.

Bit 3

Parity Enable bit. When bit 3 is a logic "1", a parity

bit is generated (transmit data) or checked

(receive

data)

between

the

last

data

word bit and the first stop bit of the serial data.

(The parity bit is used to generate an even or odd

number of 1s when the data word bits and the

parity bit are summed).

Bit 4

Even Parity Select bit. When bit 3 is a logic "1"

and bit 4 is a logic "0", an odd number of logic "1"'s

is transmitted or checked in the data word bits

and the parity bit. When bit 3 is a logic "1" and bit

4 is a logic "1" an even number of bits is

transmitted and checked.

Bit 5

Stick Parity bit. When bit 3 is a logic "1" and bit 5

is a logic "1", the parity bit is transmitted and then

detected by the receiver in the opposite state

indicated by bit 4.

Bit 6

Set Break Control bit. When bit 6 is a logic "1", the

transmit data output (TXD) is forced to the

Spacing or logic "0" state and remains there (until

reset by a low level bit 6) regardless of other

transmitter activity. This feature enables the Serial

Port to alert a terminal in a communications

system.

Bit 7

Divisor Latch Access bit (DLAB). It must be set

high (logic "1") to access the Divisor Latches of the

Baud Rate Generator during read or write

operations. It must be set low (logic "0") to access

the Receiver Buffer Register, the Transmitter

Holding Register, or the Interrupt Enable Register.

MODEM CONTROL REGISTER (MCR)

Address Offset = 4H, DLAB = X,

READ/WRITE

This 8 bit register controls the interface with the

MODEM or data set (or device emulating a

MODEM). The contents of the MODEM control

IRCC Datasheet(PDF) 44 Page - SMSC Corporation

IRCC Datasheet(HTML) 44 Page - SMSC Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79

Datasheet Download

Link URL