PI7C7300 datasheet(41/109 Pages) PERICOM

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PI7C7300A

3-PORT PCI-TO-PCI BRIDGE

ADVANCE INFORMATION

Page 41 OF 109

09/25/03 Revision 1.09

Two 32-bit I/O address ranges

Two 32-bit memory-mapped I/O (non-prefetchable memory) ranges

Two 32-bit prefetchable memory address ranges

Transactions falling within these ranges are forwarded downstream from the primary PCI

bus to the two secondary PCI buses. Transactions falling outside these ranges are

forwarded upstream from the two secondary PCI buses to the primary PCI bus.

No address translation is required in PI7C7300A. The addresses that are not marked for

downstream are always forwarded upstream. However, if an address of a transaction

initiated from S1 bus is located in the marked address range for down-stream in S2 bus

and not in the marked address range for downstream in S1 bus, the transaction will be

forwarded to S2 bus instead of primary bus. By the same token, if an address of a

transaction initiated from S2 bus is located in the marked address range for downstream

in S1 bus and not in the marked address range for downstream in S2 bus, the transaction

will be forwarded to S1 bus instead of primary bus.

5.2

I/O ADDRESS DECODING

PI7C7300A uses the following mechanisms that are defined in the configuration space to

specify the I/O address space for downstream and upstream forwarding:

I/O base and limit address registers

The ISA enable bit

The VGA mode bit

The VGA snoop bit

This section provides information on the I/O address registers and ISA mode. Section

5.4 provides information on the VGA modes.

To enable downstream forwarding of I/O transactions, the I/O enable bit must be set in

the command register in configuration space. All I/O transactions initiated on the primary

bus will be ignored if the I/O enable bit is not set. To enable upstream forwarding of I/O

transactions, the master enable bit must be set in the command register. If the master-

enable bit is not set, PI7C7300A ignores all I/O and memory transactions initiated on the

secondary bus.

The master-enable bit also allows upstream forwarding of memory transactions

if it is set.

CAUTION

If any configuration state affecting I/O transaction forwarding is changed by a

configuration write operation on the primary bus at the same time that I/O

transactions are ongoing on the secondary bus, PI7C7300A response to the secondary

bus I/O transactions is not predictable. Configure the I/O base and limit address

registers, ISA enable bit, VGA mode bit, and VGA snoop bit before setting I/O enable

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