PI7C7300 datasheet(36/109 Pages) PERICOM

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PI7C7300A

3-PORT PCI-TO-PCI BRIDGE

ADVANCE INFORMATION

Page 36 OF 109

09/25/03 Revision 1.09

For delayed read and write transactions, PI7C7300A is able to reflect the master abort

condition back to the initiator. When PI7C7300A detects a master abort in response to a

delayed transaction, and when the initiator repeats the transaction, PI7C7300A does not

respond to the transaction with DEVSEL# which induces the master abort condition back

to the initiator. The transaction is then removed from the delayed transaction queue.

When a master abort is received in response to a posted write transaction, PI7C7300A

discards the posted write data and makes no more attempts to deliver the data.

PI7C7300A sets the received-master-abort bit in the status register when the master abort

is received on the primary bus, or it sets the received master abort bit in the secondary

status register when the master abort is received on the secondary interface. When master

abort is detected in posted write transaction with both master-abort-mode bit (bit 5 of

bridge control register) and the SERR# enable bit (bit 8 of command register for

secondary bus S1 or S2) are set, PI7C7300A asserts P_SERR# if the master-abort-on-

posted-write is not set. The master-abort-on-posted-write bit is bit 4 of the P_SERR#

event disable register (offset 64h).

Note: When PI7C7300A performs a Type 1 to special cycle conversion, a master abort is

the expected termination for the special cycle on the target bus. In this case, the master

abort received bit is not set, and the Type 1 configuration transaction is disconnected

after the first data phase.

4.9.3

TARGET TERMINATION RECEIVED BY PI7C7300A

When PI7C7300A initiates a transaction on the target bus and the target responds with

DEVSEL#, the target can end the transaction with one of the following types of

termination:

Normal termination (upon de-assertion of FRAME#)

Target retry

Target disconnect

Target abort

PI7C7300A handles these terminations in different ways, depending on the type of

transaction being performed.

4.9.3.1

DELAYED WRITE TARGET TERMINATION RESPONSE

When PI7C7300A initiates a delayed write transaction, the type of target termination

received from the target can be passed back to the initiator. Table 4-7 shows the response

to each type of target termination that occurs during a delayed write transaction.

PI7C7300A repeats a delayed write transaction until one of the following conditions is

met:

PI7C7300A completes at least one data transfer.

PI7C7300A receives a master abort.

PI7C7300A receives a target abort.

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