PI7C7300 datasheet(5/109 Pages) PERICOM

5 / 109 page

PI7C7300A

3-PORT PCI-TO-PCI BRIDGE

ADVANCE INFORMATION

Page 5 OF 109

09/25/03 Revision 1.09

TABLE OF CONTENTS

INTRODUCTION .............................................................................................................................. 11

BLOCK DIAGRAM........................................................................................................................... 12

SIGNAL DEFINITIONS ................................................................................................................... 13

3.1

SIGNAL TYPES .......................................................................................................................... 13

3.2

PRIMARY BUS INTERFACE SIGNALS ................................................................................... 13

3.3

SECONDARY BUS INTERFACE SIGNALS............................................................................. 15

3.4

CLOCK SIGNALS....................................................................................................................... 17

3.5

MISCELLANEOUS SIGNALS ................................................................................................... 17

3.6

COMPACT PCI HOT-SWAP SIGNALS..................................................................................... 17

3.7

JTAG BOUNDARY SCAN SIGNALS........................................................................................ 18

3.8

POWER AND GROUND............................................................................................................. 18

3.9

PI7C7300A PBGA PIN LIST ....................................................................................................... 18

PCI BUS OPERATION ..................................................................................................................... 21

4.1

TYPES OF TRANSACTIONS..................................................................................................... 21

4.2

SINGLE ADDRESS PHASE ....................................................................................................... 22

4.3

DUAL ADDRESS PHASE........................................................................................................... 22

4.4

DEVICE SELECT (DEVSEL#) GENERATION......................................................................... 22

4.5

DATA PHASE ............................................................................................................................. 22

4.6

WRITE TRANSACTIONS .......................................................................................................... 23

4.6.1

MEMORY WRITE TRANSACTIONS.................................................................................... 23

4.6.2

MEMORY WRITE AND INVALIDATE TRANSACTIONS.................................................... 24

4.6.3

DELAYED WRITE TRANSACTIONS ................................................................................... 24

4.6.4

WRITE TRANSACTION ADDRESS BOUNDARIES ............................................................ 25

4.6.5

BUFFERING MULTIPLE WRITE TRANSACTIONS........................................................... 26

4.6.6

FAST BACK-TO-BACK WRITE TRANSACTIONS .............................................................. 26

4.7

READ TRANSACTIONS ............................................................................................................ 26

4.7.1

PREFETCHABLE READ TRANSACTIONS......................................................................... 26

4.7.2

NON-PREFETCHABLE READ TRANSACTIONS ............................................................... 27

4.7.3

READ PREFETCH ADDRESS BOUNDARIES.................................................................... 27

4.7.4

DELAYED READ REQUESTS ............................................................................................. 28

4.7.5

DELAYED READ COMPLETION WITH TARGET ............................................................. 28

4.7.6

DELAYED READ COMPLETION ON INITIATOR BUS..................................................... 29

4.7.7

FAST BACK-TO-BACK READ TRANSACTION.................................................................. 30

4.8

CONFIGURATION TRANSACTIONS ...................................................................................... 30

4.8.1

TYPE 0 ACCESS TO PI7C7300A......................................................................................... 30

4.8.2

TYPE 1 TO TYPE 0 CONVERSION ..................................................................................... 31

4.8.3

TYPE 1 TO TYPE 1 FORWARDING.................................................................................... 32

4.8.4

SPECIAL CYCLES ............................................................................................................... 33

4.9

TRANSACTION TERMINATION ............................................................................................. 34

4.9.1

MASTER TERMINATION INITIATED BY PI7C7300A ....................................................... 35

4.9.2

MASTER ABORT RECEIVED BY PI7C7300A .................................................................... 35

4.9.3

TARGET TERMINATION RECEIVED BY PI7C7300A ....................................................... 36

4.9.3.1

DELAYED WRITE TARGET TERMINATION RESPONSE........................................................ 36

4.9.3.2

POSTED WRITE TARGET TERMINATION RESPONSE ........................................................... 37

4.9.3.3

DELAYED READ TARGET TERMINATION RESPONSE ......................................................... 38

4.9.4

TARGET TERMINATION INITIATED BY PI7C7300A ....................................................... 38

4.9.4.1

TARGET RETRY............................................................................................................................ 38

4.9.4.2

TARGET DISCONNECT................................................................................................................ 39

4.9.4.3

TARGET ABORT ........................................................................................................................... 40

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